Searched refs:NUM_BANKS (Results 1 – 11 of 11) sorted by relevance
67 #define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT) macro1520 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()1526 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()1532 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()1538 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()1544 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()1550 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()1556 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()1562 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v8_0_tiling_mode_table_init()1568 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v8_0_tiling_mode_table_init()[all …]
1208 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init()1214 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init()1220 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init()1226 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init()1232 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init()1238 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v7_0_tiling_mode_table_init()1244 NUM_BANKS(ADDR_SURF_4_BANK)); in gfx_v7_0_tiling_mode_table_init()1250 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init()1256 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init()1262 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init()[all …]
194 # define NUM_BANKS(x) ((x) << 6) macro
2128 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v8_0_crtc_do_set_base()
2171 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v10_0_crtc_do_set_base()
2159 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v11_0_crtc_do_set_base()
2470 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()2480 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()2490 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()2500 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()2510 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()2520 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()2530 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()2540 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()2550 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()2560 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()[all …]
2506 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init()2512 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init()2518 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init()2524 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init()2530 NUM_BANKS(ADDR_SURF_8_BANK)); in cik_tiling_mode_table_init()2536 NUM_BANKS(ADDR_SURF_4_BANK)); in cik_tiling_mode_table_init()2542 NUM_BANKS(ADDR_SURF_2_BANK)); in cik_tiling_mode_table_init()2548 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init()2554 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init()2560 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init()[all …]
1220 # define NUM_BANKS(x) ((x) << 20) macro
1277 # define NUM_BANKS(x) ((x) << 6) macro
290 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) macro555 for (i = 0; i < NUM_BANKS; i++) { in nmk_gpio_glitch_slpm_init()573 for (i = 0; i < NUM_BANKS; i++) { in nmk_gpio_glitch_slpm_restore()1058 for (i = 0; i < NUM_BANKS; i++) { in nmk_gpio_clocks_enable()1072 for (i = 0; i < NUM_BANKS; i++) { in nmk_gpio_clocks_disable()1095 for (i = 0; i < NUM_BANKS; i++) { in nmk_gpio_wakeups_suspend()1116 for (i = 0; i < NUM_BANKS; i++) { in nmk_gpio_wakeups_resume()1140 if (gpio_bank < NUM_BANKS) { in nmk_gpio_read_pull()1670 static unsigned int slpm[NUM_BANKS]; in nmk_pmx_set()