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Searched refs:PACKET3_SET_BASE (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dvid.h114 #define PACKET3_SET_BASE 0x11 macro
Dcikd.h228 #define PACKET3_SET_BASE 0x11 macro
Dgfx_v7_0.c2826 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v7_0_cp_gfx_start()
Dgfx_v8_0.c3286 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v8_0_cp_gfx_start()
/drivers/gpu/drm/radeon/
Dnid.h1162 #define PACKET3_SET_BASE 0x11 macro
Dsid.h1601 #define PACKET3_SET_BASE 0x11 macro
Dcikd.h1701 #define PACKET3_SET_BASE 0x11 macro
Dsi.c3578 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in si_cp_start()
4449 case PACKET3_SET_BASE: in si_vm_packet3_ce_check()
4527 case PACKET3_SET_BASE: in si_vm_packet3_gfx_check()
4645 case PACKET3_SET_BASE: in si_vm_packet3_compute_check()
Devergreen_cs.c1997 case PACKET3_SET_BASE: in evergreen_packet3_check()
3308 case PACKET3_SET_BASE: in evergreen_vm_packet3_check()
Devergreend.h1548 #define PACKET3_SET_BASE 0x11 macro
Dcik.c4378 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in cik_cp_gfx_start()