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Searched refs:PHY_CONTROL (Results 1 – 6 of 6) sorted by relevance

/drivers/net/ethernet/oki-semi/pch_gbe/
Dpch_gbe_phy.c27 #define PHY_CONTROL 0x00 /* Control Register */ macro
191 pch_gbe_phy_read_reg_miic(hw, PHY_CONTROL, &phy_ctrl); in pch_gbe_phy_sw_reset()
193 pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, phy_ctrl); in pch_gbe_phy_sw_reset()
203 pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, PHY_CONTROL_DEFAULT); in pch_gbe_phy_hw_reset()
225 pch_gbe_phy_read_reg_miic(hw, PHY_CONTROL, &mii_reg); in pch_gbe_phy_power_up()
227 pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, mii_reg); in pch_gbe_phy_power_up()
244 pch_gbe_phy_read_reg_miic(hw, PHY_CONTROL, &mii_reg); in pch_gbe_phy_power_down()
246 pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, mii_reg); in pch_gbe_phy_power_down()
/drivers/net/ethernet/intel/igb/
De1000_phy.c907 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); in igb_copper_link_autoneg()
912 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); in igb_copper_link_autoneg()
1157 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); in igb_phy_force_speed_duplex_igp()
1163 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); in igb_phy_force_speed_duplex_igp()
1241 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); in igb_phy_force_speed_duplex_m88()
1247 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); in igb_phy_force_speed_duplex_m88()
2058 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); in igb_phy_sw_reset()
2063 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); in igb_phy_sw_reset()
2296 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); in igb_power_up_phy_copper()
2298 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); in igb_power_up_phy_copper()
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Digb_ethtool.c1606 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140); in igb_integrated_phy_loopback()
1608 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140); in igb_integrated_phy_loopback()
1612 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); in igb_integrated_phy_loopback()
1623 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); in igb_integrated_phy_loopback()
1753 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg); in igb_loopback_cleanup()
1756 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg); in igb_loopback_cleanup()
De1000_defines.h677 #define PHY_CONTROL 0x00 /* Control Register */ macro
/drivers/net/ethernet/apm/xgene/
Dxgene_enet_sgmac.h26 #define PHY_CONTROL(src) ((src) & GENMASK(15, 0)) macro
Dxgene_enet_sgmac.c168 wr_data = PHY_CONTROL(data); in xgene_mii_phy_write()