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Searched refs:PIPEACONF_ENABLE (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/gma500/
Dmdfld_intel_display.c265 if ((temp & PIPEACONF_ENABLE) != 0) { in mdfld_disable_crtc()
266 temp &= ~PIPEACONF_ENABLE; in mdfld_disable_crtc()
279 & PIPEACONF_ENABLE)) || pipe == 1) { in mdfld_disable_crtc()
374 if ((temp & PIPEACONF_ENABLE) == 0) { in mdfld_crtc_dpms()
399 temp &= ~PIPEACONF_ENABLE; in mdfld_crtc_dpms()
415 temp |= PIPEACONF_ENABLE; in mdfld_crtc_dpms()
451 if ((temp & PIPEACONF_ENABLE) != 0) { in mdfld_crtc_dpms()
452 temp &= ~PIPEACONF_ENABLE; in mdfld_crtc_dpms()
464 | REG_READ(PIPECCONF)) & PIPEACONF_ENABLE)) in mdfld_crtc_dpms()
858 dev_priv->pipeconf[pipe] = PIPEACONF_ENABLE; /* FIXME_JLIU7 REG_READ(pipeconf_reg); */ in mdfld_crtc_mode_set()
Doaktrail_hdmi.c362 pipeconf |= PIPEACONF_ENABLE; in oaktrail_crtc_hdmi_mode_set()
402 if ((temp & PIPEACONF_ENABLE) != 0) { in oaktrail_crtc_hdmi_dpms()
403 REG_WRITE(PIPEBCONF, temp & ~PIPEACONF_ENABLE); in oaktrail_crtc_hdmi_dpms()
409 if ((temp & PIPEACONF_ENABLE) != 0) { in oaktrail_crtc_hdmi_dpms()
410 REG_WRITE(PCH_PIPEBCONF, temp & ~PIPEACONF_ENABLE); in oaktrail_crtc_hdmi_dpms()
444 if ((temp & PIPEACONF_ENABLE) == 0) { in oaktrail_crtc_hdmi_dpms()
445 REG_WRITE(PIPEBCONF, temp | PIPEACONF_ENABLE); in oaktrail_crtc_hdmi_dpms()
451 if ((temp & PIPEACONF_ENABLE) == 0) { in oaktrail_crtc_hdmi_dpms()
452 REG_WRITE(PCH_PIPEBCONF, temp | PIPEACONF_ENABLE); in oaktrail_crtc_hdmi_dpms()
Doaktrail_crtc.c272 if ((temp & PIPEACONF_ENABLE) == 0) { in oaktrail_crtc_dpms()
274 temp | PIPEACONF_ENABLE, i); in oaktrail_crtc_dpms()
316 if ((temp & PIPEACONF_ENABLE) != 0) { in oaktrail_crtc_dpms()
318 temp & ~PIPEACONF_ENABLE, i); in oaktrail_crtc_dpms()
Dpsb_irq.c520 if (!(reg_val & PIPEACONF_ENABLE)) in psb_enable_vblank()
579 if (!(reg_val & PIPEACONF_ENABLE)) in mdfld_enable_te()
646 if (!(reg_val & PIPEACONF_ENABLE)) { in psb_get_vblank_counter()
Dgma_display.c255 if ((temp & PIPEACONF_ENABLE) == 0) in gma_crtc_dpms()
256 REG_WRITE(map->conf, temp | PIPEACONF_ENABLE); in gma_crtc_dpms()
301 if ((temp & PIPEACONF_ENABLE) != 0) { in gma_crtc_dpms()
302 REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE); in gma_crtc_dpms()
Dpsb_intel_display.c213 pipeconf |= PIPEACONF_ENABLE; in psb_intel_crtc_mode_set()
Dpsb_intel_reg.h492 #define PIPEACONF_ENABLE (1 << 31) macro
Dcdv_intel_display.c736 pipeconf |= PIPEACONF_ENABLE; in cdv_intel_crtc_mode_set()