| /drivers/video/fbdev/riva/ |
| D | nvreg.h | 126 #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
127 #define PMC_Read(reg) DEVICE_READ(PMC,reg)
128 #define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
129 #define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
130 #define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
131 #define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
133 #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
134 #define PMC_Read(reg) DEVICE_READ(PMC,reg)
135 #define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
136 #define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
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| D | nv_driver.c | 166 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in riva_get_memlen()
167 && ((NV_RD32(chip->PMC, 0x00000000)&0x0F)>=0x02)) { in riva_get_memlen()
280 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in riva_get_maxdclk()
281 && ((NV_RD32(chip->PMC,0x00000000)&0x0F) >= 0x02)) { in riva_get_maxdclk()
329 par->riva.PMC = in riva_common_setup()
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| D | riva_hw.c | 1415 LOAD_FIXED_STATE(Riva,PMC); in LoadStateExt()
1569 NV_WR32(chip->PMC, 0x00008704, 1); in LoadStateExt()
1570 NV_WR32(chip->PMC, 0x00008140, 0); in LoadStateExt()
1571 NV_WR32(chip->PMC, 0x00008920, 0); in LoadStateExt()
1572 NV_WR32(chip->PMC, 0x00008924, 0); in LoadStateExt()
1573 NV_WR32(chip->PMC, 0x00008908, 0x01ffffff); in LoadStateExt()
1574 NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff); in LoadStateExt()
1575 NV_WR32(chip->PMC, 0x00001588, 0); in LoadStateExt()
1727 NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01); in LoadStateExt()
1984 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in nv3GetConfig()
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| D | riva_hw.h | 452 volatile U032 __iomem *PMC; member
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| D | fbdev.c | 307 tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF; in riva_bl_update_status()
315 NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc); in riva_bl_update_status()
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| /drivers/video/fbdev/nvidia/ |
| D | nv_hw.c | 147 pll = NV_RD32(par->PMC, 0x4020); in nvGetClocks()
149 pll = NV_RD32(par->PMC, 0x4024); in nvGetClocks()
162 pll = NV_RD32(par->PMC, 0x4000); in nvGetClocks()
164 pll = NV_RD32(par->PMC, 0x4004); in nvGetClocks()
949 NV_WR32(par->PMC, 0x0140, 0x00000000); in NVLoadStateExt()
950 NV_WR32(par->PMC, 0x0200, 0xFFFF00FF); in NVLoadStateExt()
951 NV_WR32(par->PMC, 0x0200, 0xFFFFFFFF); in NVLoadStateExt()
1265 NV_WR32(par->PMC, 0x1700, in NVLoadStateExt()
1267 NV_WR32(par->PMC, 0x1704, 0); in NVLoadStateExt()
1268 NV_WR32(par->PMC, 0x1708, 0); in NVLoadStateExt()
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| D | nv_backlight.c | 66 tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF; in nvidia_bl_update_status()
79 NV_WR32(par->PMC, 0x10F0, tmp_pmc); in nvidia_bl_update_status()
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| D | nv_setup.c | 261 if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) { in nv10GetConfig()
262 NV_WR32(par->PMC, 0x0004, 0x01000001); in nv10GetConfig()
329 par->PMC = par->REGS + (0x00000000 / 4); in NVCommonSetup()
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| D | nv_type.h | 163 volatile u32 __iomem *PMC; member
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| /drivers/net/can/sja1000/ |
| D | Kconfig | 85 - esd CAN-PCI/PMC/266
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| /drivers/mtd/maps/ |
| D | Kconfig | 78 tristate "CFI Flash device mapped on PMC-Sierra MSP"
83 PMC-Sierra MSP eval/demo boards.
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| /drivers/platform/x86/ |
| D | Kconfig | 939 tristate "Intel PMC IPC Driver"
942 This driver provides support for PMC control on some Intel platforms.
943 The PMC is an ARC processor which defines IPC commands for communication
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| /drivers/scsi/ |
| D | Kconfig | 1732 tristate "PMC SIERRA Linux MaxRAID adapter support"
1735 This driver supports the PMC SIERRA MaxRAID adapters.
1738 tristate "PMC-Sierra SPC 8001 SAS/SATA Based Host Adapter driver"
1742 This driver supports PMC-Sierra PCIE SAS/SATA 8x6G SPC 8001 chip
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| /drivers/staging/comedi/ |
| D | Kconfig | 865 tristate "General Standards PCI-HPDI32 / PMC-HPDI32 support"
868 digital interface rs485 boards PCI-HPDI32 and PMC-HPDI32.
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| /drivers/i2c/busses/ |
| D | Kconfig | 731 tristate "PMC MSP I2C TWI Controller"
734 This driver supports the PMC TWI controller on MSP devices.
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| /drivers/usb/host/ |
| D | Kconfig | 126 tristate "EHCI support for on-chip PMC MSP71xx USB controller"
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