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Searched refs:PP_CONTROL (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/gma500/
Dpsb_lid.c40 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | POWER_TARGET_ON); in psb_lid_timer_func()
56 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & ~POWER_TARGET_ON); in psb_lid_timer_func()
Dpsb_intel_lvds.c232 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_set_power()
243 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_set_power()
277 lvds_priv->savePP_CONTROL = REG_READ(PP_CONTROL); in psb_intel_lvds_save()
328 REG_WRITE(PP_CONTROL, lvds_priv->savePP_CONTROL); in psb_intel_lvds_restore()
332 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_restore()
338 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_restore()
Dcdv_intel_dp.c390 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
393 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_vdd_on()
394 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
404 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
407 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_vdd_off()
408 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
423 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
427 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_on()
428 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
448 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_off()
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Doaktrail_lvds.c56 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in oaktrail_lvds_set_power()
67 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in oaktrail_lvds_set_power()
Dcdv_intel_lvds.c209 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in cdv_intel_lvds_set_power()
220 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in cdv_intel_lvds_set_power()
Doaktrail_device.c243 regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL); in oaktrail_save_display_registers()
272 PSB_WVDC32(0, PP_CONTROL); in oaktrail_save_display_registers()
380 PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL); in oaktrail_restore_display_registers()
Dcdv_device.c287 regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL); in cdv_save_display_registers()
366 REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL); in cdv_restore_display_registers()
Dpsb_intel_reg.h180 #define PP_CONTROL 0x61204 macro
/drivers/gpu/drm/i915/
Di915_suspend.c53 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL); in i915_save_display()
91 I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL); in i915_restore_display()
Dintel_lvds.c219 ctl_reg = PP_CONTROL; in intel_enable_lvds()
244 ctl_reg = PP_CONTROL; in intel_disable_lvds()
963 I915_WRITE(PP_CONTROL, in intel_lvds_init()
964 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); in intel_lvds_init()
Di915_reg.h3537 #define PP_CONTROL 0x61204 macro
Dintel_display.c1312 pp_reg = PP_CONTROL; in assert_panel_unlocked()