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Searched refs:PUT (Results 1 – 5 of 5) sorted by relevance

/drivers/atm/
Dsuni.c40 #define PUT(val,reg) dev->ops->phy_put(dev,val,SUNI_##reg) macro
43 PUT((GET(reg) & ~(mask)) | ((value) << (shift)),reg)
65 PUT(0,MRI); /* latch counters */ in suni_hz()
109 if (set) PUT(GET(reg) | bit,reg); \
110 else PUT(GET(reg) & ~bit,reg); \
198 PUT(GET(RPOP_RC) & ~SUNI_RPOP_RC_ENSS, RPOP_RC); in set_sonet()
199 PUT(GET(SSTB_CTRL) & ~SUNI_SSTB_CTRL_LEN16, SSTB_CTRL); in set_sonet()
200 PUT(GET(SPTB_CTRL) & ~SUNI_SPTB_CTRL_LEN16, SPTB_CTRL); in set_sonet()
212 PUT(GET(RPOP_RC) | SUNI_RPOP_RC_ENSS, RPOP_RC); in set_sdh()
213 PUT(GET(SSTB_CTRL) | SUNI_SSTB_CTRL_LEN16, SSTB_CTRL); in set_sdh()
[all …]
DuPD98402.c36 #define PUT(val,reg) dev->ops->phy_put(dev,val,uPD98402_##reg) macro
76 PUT(set[0],C11T); in set_framing()
77 PUT(set[1],C12T); in set_framing()
78 PUT(set[2],C13T); in set_framing()
79 PUT((GET(MDR) & ~uPD98402_MDR_SS_MASK) | (set[3] << in set_framing()
129 PUT(mode_reg,MDR); in set_loopback()
218 PUT(uPD98402_PFM_FJ,PCMR); /* ignore frequency adj */ in uPD98402_start()
220 PUT(~uPD98402_PCO_HECC,PCOMR); in uPD98402_start()
222 PUT(~(uPD98402_INT_PFM | uPD98402_INT_ALM | uPD98402_INT_RFO | in uPD98402_start()
Didt77105.c45 #define PUT(val,reg) dev->ops->phy_put(dev,val,IDT77105_##reg) macro
66 PUT(counter, CTRSEL); in get_counter()
132 PUT( GET(DIAG) | IDT77105_DIAG_RFLUSH, DIAG); in idt77105_restart_timer_func()
134 PUT( walk->old_mcr ,MCR); in idt77105_restart_timer_func()
175 PUT(diag,DIAG); in set_loopback()
231 PUT( in idt77105_int()
245 PUT( GET(DIAG) | IDT77105_DIAG_RFLUSH, DIAG); in idt77105_int()
298 PUT(PRIV(dev)->old_mcr, MCR); in idt77105_start()
329 PUT( GET(MCR) & ~IDT77105_MCR_EIP, MCR ); in idt77105_stop()
/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/
Dcom.fuc36 ld b32 $r9 D[$r13 + 0x4] // PUT
53 // update PUT
70 ld b32 $r9 D[$r13 + 0x4] // PUT
/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/
Dkernel.fuc417 // increment PUT