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Searched refs:REG_CTRL (Results 1 – 9 of 9) sorted by relevance

/drivers/pwm/
Dpwm-vt8500.c39 #define REG_CTRL(pwm) (((pwm) << 4) + 0x00) macro
125 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_config()
127 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_config()
146 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_enable()
148 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_enable()
159 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_disable()
161 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_disable()
174 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_set_polarity()
181 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_set_polarity()
/drivers/video/backlight/
Dlm3630a_bl.c22 #define REG_CTRL 0x00 macro
93 rval |= lm3630a_update(pchip, REG_CTRL, 0x14, pdata->leda_ctrl); in lm3630a_chip_init()
94 rval |= lm3630a_update(pchip, REG_CTRL, 0x0B, pdata->ledb_ctrl); in lm3630a_chip_init()
131 rval = lm3630a_update(pchip, REG_CTRL, 0x80, 0x00); in lm3630a_isr_func()
190 ret = lm3630a_update(pchip, REG_CTRL, 0x80, 0x00); in lm3630a_bank_a_update_status()
197 ret |= lm3630a_update(pchip, REG_CTRL, LM3630A_LEDA_ENABLE, 0); in lm3630a_bank_a_update_status()
199 ret |= lm3630a_update(pchip, REG_CTRL, in lm3630a_bank_a_update_status()
229 rval = lm3630a_update(pchip, REG_CTRL, 0x80, 0x00); in lm3630a_bank_a_get_brightness()
267 ret = lm3630a_update(pchip, REG_CTRL, 0x80, 0x00); in lm3630a_bank_b_update_status()
274 ret |= lm3630a_update(pchip, REG_CTRL, LM3630A_LEDB_ENABLE, 0); in lm3630a_bank_b_update_status()
[all …]
/drivers/i2c/busses/
Di2c-meson.c23 #define REG_CTRL 0x00 macro
141 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV_MASK, in meson_i2c_set_clk_div()
226 ctrl = readl(i2c->regs + REG_CTRL); in meson_i2c_irq()
282 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0); in meson_i2c_irq()
283 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, in meson_i2c_irq()
319 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_ACK_IGNORE, flags); in meson_i2c_xfer_msg()
330 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START); in meson_i2c_xfer_msg()
343 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0); in meson_i2c_xfer_msg()
452 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0); in meson_i2c_probe()
Di2c-efm32.c20 #define REG_CTRL 0x00 macro
423 efm32_i2c_write32(ddata, REG_CTRL, REG_CTRL_EN | in efm32_i2c_probe()
/drivers/video/fbdev/
Dxilinxfb.c64 #define REG_CTRL 1 macro
233 xilinx_fb_out32(drvdata, REG_CTRL, drvdata->reg_ctrl_default); in xilinx_fb_blank()
241 xilinx_fb_out32(drvdata, REG_CTRL, 0); in xilinx_fb_blank()
313 xilinx_fb_out32(drvdata, REG_CTRL, in xilinxfb_assign()
372 xilinx_fb_out32(drvdata, REG_CTRL, 0); in xilinxfb_assign()
396 xilinx_fb_out32(drvdata, REG_CTRL, 0); in xilinxfb_release()
/drivers/iio/adc/
Dti_am335x_adc.c165 config = tiadc_readl(adc_dev, REG_CTRL); in tiadc_irq_h()
167 tiadc_writel(adc_dev, REG_CTRL, config); in tiadc_irq_h()
179 tiadc_writel(adc_dev, REG_CTRL, (config | CNTRLREG_TSCSSENB)); in tiadc_irq_h()
563 idle = tiadc_readl(adc_dev, REG_CTRL); in tiadc_suspend()
565 tiadc_writel(adc_dev, REG_CTRL, (idle | in tiadc_suspend()
579 restore = tiadc_readl(adc_dev, REG_CTRL); in tiadc_resume()
581 tiadc_writel(adc_dev, REG_CTRL, restore); in tiadc_resume()
/drivers/mfd/
Dti_am335x_tscadc.c242 tscadc_writel(tscadc, REG_CTRL, ctrl); in ti_tscadc_probe()
256 tscadc_writel(tscadc, REG_CTRL, ctrl); in ti_tscadc_probe()
333 tscadc_writel(tscadc_dev, REG_CTRL, ctrl); in tscadc_resume()
343 tscadc_writel(tscadc_dev, REG_CTRL, ctrl); in tscadc_resume()
/drivers/spi/
Dspi-meson-spifc.c30 #define REG_CTRL 0x08 macro
260 regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB, 0); in meson_spifc_transfer_one()
270 regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB, in meson_spifc_transfer_one()
Dspi-efm32.c25 #define REG_CTRL 0x00 macro
128 (spi->mode & SPI_CPOL ? REG_CTRL_CLKPOL : 0), REG_CTRL); in efm32_spi_setup_transfer()