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Searched refs:REG_GET_FIELD (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dtonga_smc.c131 val = REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable); in tonga_is_smc_ram_running()
143 if (REG_GET_FIELD(val, SMC_RESP_0, SMC_RESP)) in wait_smu_response()
249 if (REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, cken) == 0)
601 if (REG_GET_FIELD(val, RCU_UC_EVENTS, INTERRUPTS_ENABLED)) in tonga_smu_start_in_protection_mode()
619 if (REG_GET_FIELD(val, SMU_STATUS, SMU_DONE)) in tonga_smu_start_in_protection_mode()
631 if (!REG_GET_FIELD(val, SMU_STATUS, SMU_PASS)) { in tonga_smu_start_in_protection_mode()
639 if(REG_GET_FIELD(val, FIRMWARE_FLAGS, INTERRUPTS_ENABLED)) in tonga_smu_start_in_protection_mode()
660 val = REG_GET_FIELD(val, RCU_UC_EVENTS, boot_seq_done); in tonga_smu_start_in_non_protection_mode()
699 if (REG_GET_FIELD(val, FIRMWARE_FLAGS, INTERRUPTS_ENABLED)) in tonga_smu_start_in_non_protection_mode()
719 if (!REG_GET_FIELD(val, SMU_FIRMWARE, SMU_MODE)) { in tonga_smu_start()
Dfiji_smc.c131 val = REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable); in fiji_is_smc_ram_running()
143 if (REG_GET_FIELD(val, SMC_RESP_0, SMC_RESP)) in wait_smu_response()
249 if (REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, cken) == 0)
599 if (REG_GET_FIELD(val, RCU_UC_EVENTS, INTERRUPTS_ENABLED)) in fiji_smu_start_in_protection_mode()
617 if (REG_GET_FIELD(val, SMU_STATUS, SMU_DONE)) in fiji_smu_start_in_protection_mode()
629 if (!REG_GET_FIELD(val, SMU_STATUS, SMU_PASS)) { in fiji_smu_start_in_protection_mode()
637 if(REG_GET_FIELD(val, FIRMWARE_FLAGS, INTERRUPTS_ENABLED)) in fiji_smu_start_in_protection_mode()
659 val = REG_GET_FIELD(val, RCU_UC_EVENTS, boot_seq_done); in fiji_smu_start_in_non_protection_mode()
698 if (REG_GET_FIELD(val, FIRMWARE_FLAGS, INTERRUPTS_ENABLED)) in fiji_smu_start_in_non_protection_mode()
718 if (!REG_GET_FIELD(val, SMU_FIRMWARE, SMU_MODE)) { in fiji_smu_start()
Dgmc_v8_0.c161 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { in gmc_v8_0_mc_stop()
266 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v8_0_mc_load_microcode()
294 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_mc_load_microcode()
300 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_mc_load_microcode()
406 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { in gmc_v8_0_mc_init()
412 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v8_0_mc_init()
810 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v8_0_vm_decode_fault()
811 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
816 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
821 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
Dgmc_v7_0.c111 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { in gmc_v7_0_mc_stop()
226 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v7_0_mc_load_microcode()
254 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
260 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
366 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { in gmc_v7_0_mc_init()
372 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v7_0_mc_init()
731 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v7_0_vm_decode_fault()
732 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
737 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
742 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
Diceland_smc.c167 val = REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable); in iceland_is_smc_ram_running()
179 if (REG_GET_FIELD(val, SMC_RESP_0, SMC_RESP)) in wait_smu_response()
255 if (REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, cken) == 0)
303 if (REG_GET_FIELD(val, RCU_UC_EVENTS, boot_seq_done) == 0) in iceland_smu_upload_firmware_image()
388 if (REG_GET_FIELD(val, FIRMWARE_FLAGS, INTERRUPTS_ENABLED) == 1) in iceland_smu_start_smc()
Dcz_ih.c195 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in cz_ih_get_wptr()
325 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in cz_ih_is_idle()
340 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in cz_ih_wait_for_idle()
Diceland_ih.c195 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in iceland_ih_get_wptr()
325 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in iceland_ih_is_idle()
340 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in iceland_ih_wait_for_idle()
Dtonga_ih.c206 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in tonga_ih_get_wptr()
348 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in tonga_ih_is_idle()
363 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in tonga_ih_wait_for_idle()
Ddce_v10_0.c540 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { in dce_v10_0_is_display_hung()
578 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v10_0_stop_mc_access()
587 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { in dce_v10_0_stop_mc_access()
602 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { in dce_v10_0_stop_mc_access()
607 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { in dce_v10_0_stop_mc_access()
646 if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { in dce_v10_0_resume_mc_access()
651 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { in dce_v10_0_resume_mc_access()
656 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { in dce_v10_0_resume_mc_access()
662 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) in dce_v10_0_resume_mc_access()
846 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) in dce_v10_0_line_buffer_adjust()
[all …]
Ddce_v11_0.c528 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { in dce_v11_0_is_display_hung()
566 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v11_0_stop_mc_access()
575 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { in dce_v11_0_stop_mc_access()
590 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { in dce_v11_0_stop_mc_access()
595 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { in dce_v11_0_stop_mc_access()
634 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { in dce_v11_0_resume_mc_access()
639 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { in dce_v11_0_resume_mc_access()
644 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { in dce_v11_0_resume_mc_access()
650 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) in dce_v11_0_resume_mc_access()
834 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) in dce_v11_0_line_buffer_adjust()
[all …]
Ddce_v8_0.c553 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v8_0_stop_mc_access()
562 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { in dce_v8_0_stop_mc_access()
577 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { in dce_v8_0_stop_mc_access()
582 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { in dce_v8_0_stop_mc_access()
621 if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { in dce_v8_0_resume_mc_access()
626 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { in dce_v8_0_resume_mc_access()
631 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { in dce_v8_0_resume_mc_access()
637 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) in dce_v8_0_resume_mc_access()
Dcz_smc.c57 tmp = REG_GET_FIELD(RREG32(mmSMU_MP1_SRBM2P_RESP_0), in cz_send_msg_to_smc_async()
83 tmp = REG_GET_FIELD(RREG32(mmSMU_MP1_SRBM2P_RESP_0), in cz_send_msg_to_smc()
Dgfx_v8_0.c1143 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); in gfx_v8_0_gpu_early_init()
1144 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); in gfx_v8_0_gpu_early_init()
1147 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); in gfx_v8_0_gpu_early_init()
1148 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); in gfx_v8_0_gpu_early_init()
1167 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS); in gfx_v8_0_gpu_early_init()
4084 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)) in gfx_v8_0_is_idle()
4100 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) in gfx_v8_0_wait_for_idle()
4325 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) in gfx_v8_0_soft_reset()
4331 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING)) in gfx_v8_0_soft_reset()
Dvi.c297 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK)) in vi_get_xclk()
301 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE)) in vi_get_xclk()
Dcz_dpm.c515 u32 sclk_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX), in cz_dpm_debugfs_print_current_performance_level()
517 u32 uvd_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2), in cz_dpm_debugfs_print_current_performance_level()
519 u32 vce_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2), in cz_dpm_debugfs_print_current_performance_level()
Dgfx_v7_0.c2153 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); in gfx_v7_0_gpu_init()
2154 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); in gfx_v7_0_gpu_init()
2157 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); in gfx_v7_0_gpu_init()
2158 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); in gfx_v7_0_gpu_init()
Damdgpu.h2189 #define REG_GET_FIELD(value, reg, field) \ macro