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Searched refs:REG_RMW (Results 1 – 11 of 11) sorted by relevance

/drivers/net/wireless/ath/ath9k/
Dar9003_wow.c161 REG_RMW(ah, AR_WOW_LENGTH1, set, clr); in ath9k_hw_wow_apply_pattern()
166 REG_RMW(ah, AR_WOW_LENGTH2, set, clr); in ath9k_hw_wow_apply_pattern()
171 REG_RMW(ah, AR_WOW_LENGTH3, set, clr); in ath9k_hw_wow_apply_pattern()
176 REG_RMW(ah, AR_WOW_LENGTH4, set, clr); in ath9k_hw_wow_apply_pattern()
229 REG_RMW(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR, in ath9k_hw_wow_wakeup()
Deeprom_4k.c776 REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, in ath9k_hw_4k_set_gain()
779 REG_RMW(ah, AR_PHY_TIMING_CTRL4(0), in ath9k_hw_4k_set_gain()
1046 REG_RMW(ah, AR_PHY_RF_CTL4, in ath9k_hw_4k_set_board_values()
1090 REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr); in ath9k_hw_4k_set_board_values()
1091 REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr); in ath9k_hw_4k_set_board_values()
1092 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr); in ath9k_hw_4k_set_board_values()
1097 REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr); in ath9k_hw_4k_set_board_values()
1102 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr); in ath9k_hw_4k_set_board_values()
1103 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr); in ath9k_hw_4k_set_board_values()
Dhw.c1130 REG_RMW(ah, AR_USEC, in ath9k_hw_init_global_settings()
1186 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); in ath9k_hw_set_dma()
1203 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); in ath9k_hw_set_dma()
1271 REG_RMW(ah, AR_STA_ID1, set, mask); in ath9k_hw_set_operating_mode()
1681 REG_RMW(ah, AR_STA_ID1, macStaId1 in ath9k_hw_reset_opmode()
1743 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); in ath9k_hw_init_desc()
2640 REG_RMW(ah, addr, (type << gpio_shift), in ath9k_hw_gpio_cfg_output_mux()
2659 REG_RMW(ah, AR7010_GPIO_OE, in ath9k_hw_cfg_gpio_input()
2666 REG_RMW(ah, in ath9k_hw_cfg_gpio_input()
2708 REG_RMW(ah, AR7010_GPIO_OE, in ath9k_hw_cfg_output()
[all …]
Dcalib.c261 REG_RMW(ah, ah->nf_regs[i], in ath9k_hw_loadnf()
317 REG_RMW(ah, ah->nf_regs[i], in ath9k_hw_loadnf()
Dhw.h88 #define REG_RMW(_ah, _reg, _set, _clr) \ macro
124 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
128 REG_RMW(_a, _r, (_f), 0)
130 REG_RMW(_a, _r, 0, (_f))
Dar9002_phy.c432 REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000); in ar9002_hw_set_bt_ant_diversity()
451 REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000); in ar9002_hw_set_bt_ant_diversity()
Dar9003_phy.c836 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, in ar9003_doubler_fix()
839 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, in ar9003_doubler_fix()
842 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, in ar9003_doubler_fix()
869 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0, in ar9003_doubler_fix()
872 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0, in ar9003_doubler_fix()
875 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0, in ar9003_doubler_fix()
Deeprom_def.c487 REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain()
490 REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain()
504 REG_RMW(ah, AR_PHY_RXGAIN + regChainOffset, in ath9k_hw_def_set_gain()
507 REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain()
Dbtcoex.c343 REG_RMW(ah, AR_GPIO_PDPU, in ath9k_hw_btcoex_enable()
Dar9003_eeprom.c4741 REG_RMW(ah, AR_PHY_TPC_11_B0, in ar9003_hw_power_control_override()
4745 REG_RMW(ah, AR_PHY_TPC_11_B1, in ar9003_hw_power_control_override()
4749 REG_RMW(ah, AR_PHY_TPC_11_B2, in ar9003_hw_power_control_override()
4754 REG_RMW(ah, AR_PHY_TPC_6_B0, in ar9003_hw_power_control_override()
4758 REG_RMW(ah, AR_PHY_TPC_6_B1, in ar9003_hw_power_control_override()
4762 REG_RMW(ah, AR_PHY_TPC_6_B2, in ar9003_hw_power_control_override()
Deeprom.c30 REG_RMW(ah, reg, ((val << shift) & mask), mask); in ath9k_hw_analog_shift_rmw()