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Searched refs:RREG8 (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/mgag200/
Dmgag200_mode.c91 status = RREG8(MGAREG_Status + 2); in mga_wait_busy()
313 tmp = RREG8(MGAREG_CRTC_DATA); in mga_g200wb_set_plls()
320 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()
325 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()
330 tmp = RREG8(MGAREG_MEM_MISC_READ); in mga_g200wb_set_plls()
335 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()
343 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()
358 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()
366 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()
372 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()
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Dmgag200_i2c.c38 return RREG8(DAC_DATA); in mga_i2c_read_gpio()
46 tmp = (RREG8(DAC_DATA) & mask) | val; in mga_i2c_set_gpio()
Dmgag200_drv.h44 #define RREG8(reg) ioread8(((void __iomem *)mdev->rmmio) + (reg)) macro
54 RREG8(0x1fda); \
/drivers/gpu/drm/cirrus/
Dcirrus_drv.h38 #define RREG8(reg) ioread8(((void __iomem *)cdev->rmmio) + (reg)) macro
79 RREG8(VGA_DAC_MASK); \
80 RREG8(VGA_DAC_MASK); \
81 RREG8(VGA_DAC_MASK); \
82 RREG8(VGA_DAC_MASK); \
Dcirrus_mode.c86 sr01 |= RREG8(SEQ_DATA) & ~0x20; in cirrus_crtc_dpms()
90 gr0e |= RREG8(GFX_DATA) & ~0x06; in cirrus_crtc_dpms()
117 tmp = RREG8(CRT_DATA); in cirrus_set_start_address()
123 tmp = RREG8(CRT_DATA); in cirrus_set_start_address()
269 sr07 = RREG8(SEQ_DATA); in cirrus_crtc_mode_set()
/drivers/gpu/drm/radeon/
Dradeon_legacy_tv.c290 if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold) in radeon_wait_pll_lock()
Dr100.c3769 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); in r100_mc_stop()
3822 tmp = RREG8(R_0003C2_GENMO_WT); in r100_vga_render_disable()
Dradeon_combios.c1147 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; in radeon_legacy_get_lvds_info_from_regs()
Dradeon.h2522 #define RREG8(reg) readb((rdev->rmmio) + (reg)) macro