Searched refs:RS480_GART_CACHE_CNTRL (Results 1 – 4 of 4) sorted by relevance
65 WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); in rs400_gart_tlb_flush()67 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); in rs400_gart_tlb_flush()73 WREG32_MC(RS480_GART_CACHE_CNTRL, 0); in rs400_gart_tlb_flush()349 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); in rs400_debugfs_gart_info()
957 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); in radeon_set_igpgart()963 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, in radeon_set_igpgart()967 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); in radeon_set_igpgart()973 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0); in radeon_set_igpgart()
146 #define RS480_GART_CACHE_CNTRL 0x2e macro
580 #define RS480_GART_CACHE_CNTRL 0x2e macro