Searched refs:RS480_MC_MISC_CNTL (Results 1 – 4 of 4) sorted by relevance
176 tmp = RREG32_MC(RS480_MC_MISC_CNTL); in rs400_gart_enable()178 WREG32_MC(RS480_MC_MISC_CNTL, tmp); in rs400_gart_enable()180 tmp = RREG32_MC(RS480_MC_MISC_CNTL); in rs400_gart_enable()182 WREG32_MC(RS480_MC_MISC_CNTL, tmp); in rs400_gart_enable()343 tmp = RREG32_MC(RS480_MC_MISC_CNTL); in rs400_debugfs_gart_info()
133 #define RS480_MC_MISC_CNTL 0x18 macro
919 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL); in radeon_set_igpgart()922 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN | in radeon_set_igpgart()925 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); in radeon_set_igpgart()
565 #define RS480_MC_MISC_CNTL 0x18 macro