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1 /*
2  * Driver for sunxi SD/MMC host controllers
3  * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
4  * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
5  * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
6  * (C) Copyright 2013-2014 David Lanzend�rfer <david.lanzendoerfer@o2s.ch>
7  * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  */
14 
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/io.h>
18 #include <linux/device.h>
19 #include <linux/interrupt.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22 
23 #include <linux/clk.h>
24 #include <linux/gpio.h>
25 #include <linux/platform_device.h>
26 #include <linux/spinlock.h>
27 #include <linux/scatterlist.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/slab.h>
30 #include <linux/reset.h>
31 
32 #include <linux/of_address.h>
33 #include <linux/of_gpio.h>
34 #include <linux/of_platform.h>
35 
36 #include <linux/mmc/host.h>
37 #include <linux/mmc/sd.h>
38 #include <linux/mmc/sdio.h>
39 #include <linux/mmc/mmc.h>
40 #include <linux/mmc/core.h>
41 #include <linux/mmc/card.h>
42 #include <linux/mmc/slot-gpio.h>
43 
44 /* register offset definitions */
45 #define SDXC_REG_GCTRL	(0x00) /* SMC Global Control Register */
46 #define SDXC_REG_CLKCR	(0x04) /* SMC Clock Control Register */
47 #define SDXC_REG_TMOUT	(0x08) /* SMC Time Out Register */
48 #define SDXC_REG_WIDTH	(0x0C) /* SMC Bus Width Register */
49 #define SDXC_REG_BLKSZ	(0x10) /* SMC Block Size Register */
50 #define SDXC_REG_BCNTR	(0x14) /* SMC Byte Count Register */
51 #define SDXC_REG_CMDR	(0x18) /* SMC Command Register */
52 #define SDXC_REG_CARG	(0x1C) /* SMC Argument Register */
53 #define SDXC_REG_RESP0	(0x20) /* SMC Response Register 0 */
54 #define SDXC_REG_RESP1	(0x24) /* SMC Response Register 1 */
55 #define SDXC_REG_RESP2	(0x28) /* SMC Response Register 2 */
56 #define SDXC_REG_RESP3	(0x2C) /* SMC Response Register 3 */
57 #define SDXC_REG_IMASK	(0x30) /* SMC Interrupt Mask Register */
58 #define SDXC_REG_MISTA	(0x34) /* SMC Masked Interrupt Status Register */
59 #define SDXC_REG_RINTR	(0x38) /* SMC Raw Interrupt Status Register */
60 #define SDXC_REG_STAS	(0x3C) /* SMC Status Register */
61 #define SDXC_REG_FTRGL	(0x40) /* SMC FIFO Threshold Watermark Registe */
62 #define SDXC_REG_FUNS	(0x44) /* SMC Function Select Register */
63 #define SDXC_REG_CBCR	(0x48) /* SMC CIU Byte Count Register */
64 #define SDXC_REG_BBCR	(0x4C) /* SMC BIU Byte Count Register */
65 #define SDXC_REG_DBGC	(0x50) /* SMC Debug Enable Register */
66 #define SDXC_REG_HWRST	(0x78) /* SMC Card Hardware Reset for Register */
67 #define SDXC_REG_DMAC	(0x80) /* SMC IDMAC Control Register */
68 #define SDXC_REG_DLBA	(0x84) /* SMC IDMAC Descriptor List Base Addre */
69 #define SDXC_REG_IDST	(0x88) /* SMC IDMAC Status Register */
70 #define SDXC_REG_IDIE	(0x8C) /* SMC IDMAC Interrupt Enable Register */
71 #define SDXC_REG_CHDA	(0x90)
72 #define SDXC_REG_CBDA	(0x94)
73 
74 #define mmc_readl(host, reg) \
75 	readl((host)->reg_base + SDXC_##reg)
76 #define mmc_writel(host, reg, value) \
77 	writel((value), (host)->reg_base + SDXC_##reg)
78 
79 /* global control register bits */
80 #define SDXC_SOFT_RESET			BIT(0)
81 #define SDXC_FIFO_RESET			BIT(1)
82 #define SDXC_DMA_RESET			BIT(2)
83 #define SDXC_INTERRUPT_ENABLE_BIT	BIT(4)
84 #define SDXC_DMA_ENABLE_BIT		BIT(5)
85 #define SDXC_DEBOUNCE_ENABLE_BIT	BIT(8)
86 #define SDXC_POSEDGE_LATCH_DATA		BIT(9)
87 #define SDXC_DDR_MODE			BIT(10)
88 #define SDXC_MEMORY_ACCESS_DONE		BIT(29)
89 #define SDXC_ACCESS_DONE_DIRECT		BIT(30)
90 #define SDXC_ACCESS_BY_AHB		BIT(31)
91 #define SDXC_ACCESS_BY_DMA		(0 << 31)
92 #define SDXC_HARDWARE_RESET \
93 	(SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
94 
95 /* clock control bits */
96 #define SDXC_CARD_CLOCK_ON		BIT(16)
97 #define SDXC_LOW_POWER_ON		BIT(17)
98 
99 /* bus width */
100 #define SDXC_WIDTH1			0
101 #define SDXC_WIDTH4			1
102 #define SDXC_WIDTH8			2
103 
104 /* smc command bits */
105 #define SDXC_RESP_EXPIRE		BIT(6)
106 #define SDXC_LONG_RESPONSE		BIT(7)
107 #define SDXC_CHECK_RESPONSE_CRC		BIT(8)
108 #define SDXC_DATA_EXPIRE		BIT(9)
109 #define SDXC_WRITE			BIT(10)
110 #define SDXC_SEQUENCE_MODE		BIT(11)
111 #define SDXC_SEND_AUTO_STOP		BIT(12)
112 #define SDXC_WAIT_PRE_OVER		BIT(13)
113 #define SDXC_STOP_ABORT_CMD		BIT(14)
114 #define SDXC_SEND_INIT_SEQUENCE		BIT(15)
115 #define SDXC_UPCLK_ONLY			BIT(21)
116 #define SDXC_READ_CEATA_DEV		BIT(22)
117 #define SDXC_CCS_EXPIRE			BIT(23)
118 #define SDXC_ENABLE_BIT_BOOT		BIT(24)
119 #define SDXC_ALT_BOOT_OPTIONS		BIT(25)
120 #define SDXC_BOOT_ACK_EXPIRE		BIT(26)
121 #define SDXC_BOOT_ABORT			BIT(27)
122 #define SDXC_VOLTAGE_SWITCH	        BIT(28)
123 #define SDXC_USE_HOLD_REGISTER	        BIT(29)
124 #define SDXC_START			BIT(31)
125 
126 /* interrupt bits */
127 #define SDXC_RESP_ERROR			BIT(1)
128 #define SDXC_COMMAND_DONE		BIT(2)
129 #define SDXC_DATA_OVER			BIT(3)
130 #define SDXC_TX_DATA_REQUEST		BIT(4)
131 #define SDXC_RX_DATA_REQUEST		BIT(5)
132 #define SDXC_RESP_CRC_ERROR		BIT(6)
133 #define SDXC_DATA_CRC_ERROR		BIT(7)
134 #define SDXC_RESP_TIMEOUT		BIT(8)
135 #define SDXC_DATA_TIMEOUT		BIT(9)
136 #define SDXC_VOLTAGE_CHANGE_DONE	BIT(10)
137 #define SDXC_FIFO_RUN_ERROR		BIT(11)
138 #define SDXC_HARD_WARE_LOCKED		BIT(12)
139 #define SDXC_START_BIT_ERROR		BIT(13)
140 #define SDXC_AUTO_COMMAND_DONE		BIT(14)
141 #define SDXC_END_BIT_ERROR		BIT(15)
142 #define SDXC_SDIO_INTERRUPT		BIT(16)
143 #define SDXC_CARD_INSERT		BIT(30)
144 #define SDXC_CARD_REMOVE		BIT(31)
145 #define SDXC_INTERRUPT_ERROR_BIT \
146 	(SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
147 	 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
148 	 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
149 #define SDXC_INTERRUPT_DONE_BIT \
150 	(SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
151 	 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
152 
153 /* status */
154 #define SDXC_RXWL_FLAG			BIT(0)
155 #define SDXC_TXWL_FLAG			BIT(1)
156 #define SDXC_FIFO_EMPTY			BIT(2)
157 #define SDXC_FIFO_FULL			BIT(3)
158 #define SDXC_CARD_PRESENT		BIT(8)
159 #define SDXC_CARD_DATA_BUSY		BIT(9)
160 #define SDXC_DATA_FSM_BUSY		BIT(10)
161 #define SDXC_DMA_REQUEST		BIT(31)
162 #define SDXC_FIFO_SIZE			16
163 
164 /* Function select */
165 #define SDXC_CEATA_ON			(0xceaa << 16)
166 #define SDXC_SEND_IRQ_RESPONSE		BIT(0)
167 #define SDXC_SDIO_READ_WAIT		BIT(1)
168 #define SDXC_ABORT_READ_DATA		BIT(2)
169 #define SDXC_SEND_CCSD			BIT(8)
170 #define SDXC_SEND_AUTO_STOPCCSD		BIT(9)
171 #define SDXC_CEATA_DEV_IRQ_ENABLE	BIT(10)
172 
173 /* IDMA controller bus mod bit field */
174 #define SDXC_IDMAC_SOFT_RESET		BIT(0)
175 #define SDXC_IDMAC_FIX_BURST		BIT(1)
176 #define SDXC_IDMAC_IDMA_ON		BIT(7)
177 #define SDXC_IDMAC_REFETCH_DES		BIT(31)
178 
179 /* IDMA status bit field */
180 #define SDXC_IDMAC_TRANSMIT_INTERRUPT		BIT(0)
181 #define SDXC_IDMAC_RECEIVE_INTERRUPT		BIT(1)
182 #define SDXC_IDMAC_FATAL_BUS_ERROR		BIT(2)
183 #define SDXC_IDMAC_DESTINATION_INVALID		BIT(4)
184 #define SDXC_IDMAC_CARD_ERROR_SUM		BIT(5)
185 #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM		BIT(8)
186 #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM	BIT(9)
187 #define SDXC_IDMAC_HOST_ABORT_INTERRUPT		BIT(10)
188 #define SDXC_IDMAC_IDLE				(0 << 13)
189 #define SDXC_IDMAC_SUSPEND			(1 << 13)
190 #define SDXC_IDMAC_DESC_READ			(2 << 13)
191 #define SDXC_IDMAC_DESC_CHECK			(3 << 13)
192 #define SDXC_IDMAC_READ_REQUEST_WAIT		(4 << 13)
193 #define SDXC_IDMAC_WRITE_REQUEST_WAIT		(5 << 13)
194 #define SDXC_IDMAC_READ				(6 << 13)
195 #define SDXC_IDMAC_WRITE			(7 << 13)
196 #define SDXC_IDMAC_DESC_CLOSE			(8 << 13)
197 
198 /*
199 * If the idma-des-size-bits of property is ie 13, bufsize bits are:
200 *  Bits  0-12: buf1 size
201 *  Bits 13-25: buf2 size
202 *  Bits 26-31: not used
203 * Since we only ever set buf1 size, we can simply store it directly.
204 */
205 #define SDXC_IDMAC_DES0_DIC	BIT(1)  /* disable interrupt on completion */
206 #define SDXC_IDMAC_DES0_LD	BIT(2)  /* last descriptor */
207 #define SDXC_IDMAC_DES0_FD	BIT(3)  /* first descriptor */
208 #define SDXC_IDMAC_DES0_CH	BIT(4)  /* chain mode */
209 #define SDXC_IDMAC_DES0_ER	BIT(5)  /* end of ring */
210 #define SDXC_IDMAC_DES0_CES	BIT(30) /* card error summary */
211 #define SDXC_IDMAC_DES0_OWN	BIT(31) /* 1-idma owns it, 0-host owns it */
212 
213 #define SDXC_CLK_400K		0
214 #define SDXC_CLK_25M		1
215 #define SDXC_CLK_50M		2
216 #define SDXC_CLK_50M_DDR	3
217 
218 struct sunxi_mmc_clk_delay {
219 	u32 output;
220 	u32 sample;
221 };
222 
223 struct sunxi_idma_des {
224 	u32	config;
225 	u32	buf_size;
226 	u32	buf_addr_ptr1;
227 	u32	buf_addr_ptr2;
228 };
229 
230 struct sunxi_mmc_host {
231 	struct mmc_host	*mmc;
232 	struct reset_control *reset;
233 
234 	/* IO mapping base */
235 	void __iomem	*reg_base;
236 
237 	/* clock management */
238 	struct clk	*clk_ahb;
239 	struct clk	*clk_mmc;
240 	struct clk	*clk_sample;
241 	struct clk	*clk_output;
242 	const struct sunxi_mmc_clk_delay *clk_delays;
243 
244 	/* irq */
245 	spinlock_t	lock;
246 	int		irq;
247 	u32		int_sum;
248 	u32		sdio_imask;
249 
250 	/* dma */
251 	u32		idma_des_size_bits;
252 	dma_addr_t	sg_dma;
253 	void		*sg_cpu;
254 	bool		wait_dma;
255 
256 	struct mmc_request *mrq;
257 	struct mmc_request *manual_stop_mrq;
258 	int		ferror;
259 };
260 
sunxi_mmc_reset_host(struct sunxi_mmc_host * host)261 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
262 {
263 	unsigned long expire = jiffies + msecs_to_jiffies(250);
264 	u32 rval;
265 
266 	mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);
267 	do {
268 		rval = mmc_readl(host, REG_GCTRL);
269 	} while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
270 
271 	if (rval & SDXC_HARDWARE_RESET) {
272 		dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
273 		return -EIO;
274 	}
275 
276 	return 0;
277 }
278 
sunxi_mmc_init_host(struct mmc_host * mmc)279 static int sunxi_mmc_init_host(struct mmc_host *mmc)
280 {
281 	u32 rval;
282 	struct sunxi_mmc_host *host = mmc_priv(mmc);
283 
284 	if (sunxi_mmc_reset_host(host))
285 		return -EIO;
286 
287 	mmc_writel(host, REG_FTRGL, 0x20070008);
288 	mmc_writel(host, REG_TMOUT, 0xffffffff);
289 	mmc_writel(host, REG_IMASK, host->sdio_imask);
290 	mmc_writel(host, REG_RINTR, 0xffffffff);
291 	mmc_writel(host, REG_DBGC, 0xdeb);
292 	mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
293 	mmc_writel(host, REG_DLBA, host->sg_dma);
294 
295 	rval = mmc_readl(host, REG_GCTRL);
296 	rval |= SDXC_INTERRUPT_ENABLE_BIT;
297 	rval &= ~SDXC_ACCESS_DONE_DIRECT;
298 	mmc_writel(host, REG_GCTRL, rval);
299 
300 	return 0;
301 }
302 
sunxi_mmc_init_idma_des(struct sunxi_mmc_host * host,struct mmc_data * data)303 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
304 				    struct mmc_data *data)
305 {
306 	struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
307 	dma_addr_t next_desc = host->sg_dma;
308 	int i, max_len = (1 << host->idma_des_size_bits);
309 
310 	for (i = 0; i < data->sg_len; i++) {
311 		pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN |
312 				 SDXC_IDMAC_DES0_DIC;
313 
314 		if (data->sg[i].length == max_len)
315 			pdes[i].buf_size = 0; /* 0 == max_len */
316 		else
317 			pdes[i].buf_size = data->sg[i].length;
318 
319 		next_desc += sizeof(struct sunxi_idma_des);
320 		pdes[i].buf_addr_ptr1 = sg_dma_address(&data->sg[i]);
321 		pdes[i].buf_addr_ptr2 = (u32)next_desc;
322 	}
323 
324 	pdes[0].config |= SDXC_IDMAC_DES0_FD;
325 	pdes[i - 1].config |= SDXC_IDMAC_DES0_LD | SDXC_IDMAC_DES0_ER;
326 	pdes[i - 1].config &= ~SDXC_IDMAC_DES0_DIC;
327 	pdes[i - 1].buf_addr_ptr2 = 0;
328 
329 	/*
330 	 * Avoid the io-store starting the idmac hitting io-mem before the
331 	 * descriptors hit the main-mem.
332 	 */
333 	wmb();
334 }
335 
sunxi_mmc_get_dma_dir(struct mmc_data * data)336 static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data)
337 {
338 	if (data->flags & MMC_DATA_WRITE)
339 		return DMA_TO_DEVICE;
340 	else
341 		return DMA_FROM_DEVICE;
342 }
343 
sunxi_mmc_map_dma(struct sunxi_mmc_host * host,struct mmc_data * data)344 static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
345 			     struct mmc_data *data)
346 {
347 	u32 i, dma_len;
348 	struct scatterlist *sg;
349 
350 	dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
351 			     sunxi_mmc_get_dma_dir(data));
352 	if (dma_len == 0) {
353 		dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
354 		return -ENOMEM;
355 	}
356 
357 	for_each_sg(data->sg, sg, data->sg_len, i) {
358 		if (sg->offset & 3 || sg->length & 3) {
359 			dev_err(mmc_dev(host->mmc),
360 				"unaligned scatterlist: os %x length %d\n",
361 				sg->offset, sg->length);
362 			return -EINVAL;
363 		}
364 	}
365 
366 	return 0;
367 }
368 
sunxi_mmc_start_dma(struct sunxi_mmc_host * host,struct mmc_data * data)369 static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
370 				struct mmc_data *data)
371 {
372 	u32 rval;
373 
374 	sunxi_mmc_init_idma_des(host, data);
375 
376 	rval = mmc_readl(host, REG_GCTRL);
377 	rval |= SDXC_DMA_ENABLE_BIT;
378 	mmc_writel(host, REG_GCTRL, rval);
379 	rval |= SDXC_DMA_RESET;
380 	mmc_writel(host, REG_GCTRL, rval);
381 
382 	mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
383 
384 	if (!(data->flags & MMC_DATA_WRITE))
385 		mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
386 
387 	mmc_writel(host, REG_DMAC,
388 		   SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
389 }
390 
sunxi_mmc_send_manual_stop(struct sunxi_mmc_host * host,struct mmc_request * req)391 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
392 				       struct mmc_request *req)
393 {
394 	u32 arg, cmd_val, ri;
395 	unsigned long expire = jiffies + msecs_to_jiffies(1000);
396 
397 	cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
398 		  SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
399 
400 	if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
401 		cmd_val |= SD_IO_RW_DIRECT;
402 		arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
403 		      ((req->cmd->arg >> 28) & 0x7);
404 	} else {
405 		cmd_val |= MMC_STOP_TRANSMISSION;
406 		arg = 0;
407 	}
408 
409 	mmc_writel(host, REG_CARG, arg);
410 	mmc_writel(host, REG_CMDR, cmd_val);
411 
412 	do {
413 		ri = mmc_readl(host, REG_RINTR);
414 	} while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
415 		 time_before(jiffies, expire));
416 
417 	if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
418 		dev_err(mmc_dev(host->mmc), "send stop command failed\n");
419 		if (req->stop)
420 			req->stop->resp[0] = -ETIMEDOUT;
421 	} else {
422 		if (req->stop)
423 			req->stop->resp[0] = mmc_readl(host, REG_RESP0);
424 	}
425 
426 	mmc_writel(host, REG_RINTR, 0xffff);
427 }
428 
sunxi_mmc_dump_errinfo(struct sunxi_mmc_host * host)429 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
430 {
431 	struct mmc_command *cmd = host->mrq->cmd;
432 	struct mmc_data *data = host->mrq->data;
433 
434 	/* For some cmds timeout is normal with sd/mmc cards */
435 	if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
436 		SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
437 				      cmd->opcode == SD_IO_RW_DIRECT))
438 		return;
439 
440 	dev_err(mmc_dev(host->mmc),
441 		"smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
442 		host->mmc->index, cmd->opcode,
443 		data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
444 		host->int_sum & SDXC_RESP_ERROR     ? " RE"     : "",
445 		host->int_sum & SDXC_RESP_CRC_ERROR  ? " RCE"    : "",
446 		host->int_sum & SDXC_DATA_CRC_ERROR  ? " DCE"    : "",
447 		host->int_sum & SDXC_RESP_TIMEOUT ? " RTO"    : "",
448 		host->int_sum & SDXC_DATA_TIMEOUT ? " DTO"    : "",
449 		host->int_sum & SDXC_FIFO_RUN_ERROR  ? " FE"     : "",
450 		host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL"     : "",
451 		host->int_sum & SDXC_START_BIT_ERROR ? " SBE"    : "",
452 		host->int_sum & SDXC_END_BIT_ERROR   ? " EBE"    : ""
453 		);
454 }
455 
456 /* Called in interrupt context! */
sunxi_mmc_finalize_request(struct sunxi_mmc_host * host)457 static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
458 {
459 	struct mmc_request *mrq = host->mrq;
460 	struct mmc_data *data = mrq->data;
461 	u32 rval;
462 
463 	mmc_writel(host, REG_IMASK, host->sdio_imask);
464 	mmc_writel(host, REG_IDIE, 0);
465 
466 	if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
467 		sunxi_mmc_dump_errinfo(host);
468 		mrq->cmd->error = -ETIMEDOUT;
469 
470 		if (data) {
471 			data->error = -ETIMEDOUT;
472 			host->manual_stop_mrq = mrq;
473 		}
474 
475 		if (mrq->stop)
476 			mrq->stop->error = -ETIMEDOUT;
477 	} else {
478 		if (mrq->cmd->flags & MMC_RSP_136) {
479 			mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
480 			mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
481 			mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
482 			mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
483 		} else {
484 			mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
485 		}
486 
487 		if (data)
488 			data->bytes_xfered = data->blocks * data->blksz;
489 	}
490 
491 	if (data) {
492 		mmc_writel(host, REG_IDST, 0x337);
493 		mmc_writel(host, REG_DMAC, 0);
494 		rval = mmc_readl(host, REG_GCTRL);
495 		rval |= SDXC_DMA_RESET;
496 		mmc_writel(host, REG_GCTRL, rval);
497 		rval &= ~SDXC_DMA_ENABLE_BIT;
498 		mmc_writel(host, REG_GCTRL, rval);
499 		rval |= SDXC_FIFO_RESET;
500 		mmc_writel(host, REG_GCTRL, rval);
501 		dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
502 				     sunxi_mmc_get_dma_dir(data));
503 	}
504 
505 	mmc_writel(host, REG_RINTR, 0xffff);
506 
507 	host->mrq = NULL;
508 	host->int_sum = 0;
509 	host->wait_dma = false;
510 
511 	return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
512 }
513 
sunxi_mmc_irq(int irq,void * dev_id)514 static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
515 {
516 	struct sunxi_mmc_host *host = dev_id;
517 	struct mmc_request *mrq;
518 	u32 msk_int, idma_int;
519 	bool finalize = false;
520 	bool sdio_int = false;
521 	irqreturn_t ret = IRQ_HANDLED;
522 
523 	spin_lock(&host->lock);
524 
525 	idma_int  = mmc_readl(host, REG_IDST);
526 	msk_int   = mmc_readl(host, REG_MISTA);
527 
528 	dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
529 		host->mrq, msk_int, idma_int);
530 
531 	mrq = host->mrq;
532 	if (mrq) {
533 		if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
534 			host->wait_dma = false;
535 
536 		host->int_sum |= msk_int;
537 
538 		/* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
539 		if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
540 				!(host->int_sum & SDXC_COMMAND_DONE))
541 			mmc_writel(host, REG_IMASK,
542 				   host->sdio_imask | SDXC_COMMAND_DONE);
543 		/* Don't wait for dma on error */
544 		else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
545 			finalize = true;
546 		else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
547 				!host->wait_dma)
548 			finalize = true;
549 	}
550 
551 	if (msk_int & SDXC_SDIO_INTERRUPT)
552 		sdio_int = true;
553 
554 	mmc_writel(host, REG_RINTR, msk_int);
555 	mmc_writel(host, REG_IDST, idma_int);
556 
557 	if (finalize)
558 		ret = sunxi_mmc_finalize_request(host);
559 
560 	spin_unlock(&host->lock);
561 
562 	if (finalize && ret == IRQ_HANDLED)
563 		mmc_request_done(host->mmc, mrq);
564 
565 	if (sdio_int)
566 		mmc_signal_sdio_irq(host->mmc);
567 
568 	return ret;
569 }
570 
sunxi_mmc_handle_manual_stop(int irq,void * dev_id)571 static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
572 {
573 	struct sunxi_mmc_host *host = dev_id;
574 	struct mmc_request *mrq;
575 	unsigned long iflags;
576 
577 	spin_lock_irqsave(&host->lock, iflags);
578 	mrq = host->manual_stop_mrq;
579 	spin_unlock_irqrestore(&host->lock, iflags);
580 
581 	if (!mrq) {
582 		dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
583 		return IRQ_HANDLED;
584 	}
585 
586 	dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
587 
588 	/*
589 	 * We will never have more than one outstanding request,
590 	 * and we do not complete the request until after
591 	 * we've cleared host->manual_stop_mrq so we do not need to
592 	 * spin lock this function.
593 	 * Additionally we have wait states within this function
594 	 * so having it in a lock is a very bad idea.
595 	 */
596 	sunxi_mmc_send_manual_stop(host, mrq);
597 
598 	spin_lock_irqsave(&host->lock, iflags);
599 	host->manual_stop_mrq = NULL;
600 	spin_unlock_irqrestore(&host->lock, iflags);
601 
602 	mmc_request_done(host->mmc, mrq);
603 
604 	return IRQ_HANDLED;
605 }
606 
sunxi_mmc_oclk_onoff(struct sunxi_mmc_host * host,u32 oclk_en)607 static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
608 {
609 	unsigned long expire = jiffies + msecs_to_jiffies(750);
610 	u32 rval;
611 
612 	rval = mmc_readl(host, REG_CLKCR);
613 	rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON);
614 
615 	if (oclk_en)
616 		rval |= SDXC_CARD_CLOCK_ON;
617 
618 	mmc_writel(host, REG_CLKCR, rval);
619 
620 	rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
621 	mmc_writel(host, REG_CMDR, rval);
622 
623 	do {
624 		rval = mmc_readl(host, REG_CMDR);
625 	} while (time_before(jiffies, expire) && (rval & SDXC_START));
626 
627 	/* clear irq status bits set by the command */
628 	mmc_writel(host, REG_RINTR,
629 		   mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
630 
631 	if (rval & SDXC_START) {
632 		dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
633 		return -EIO;
634 	}
635 
636 	return 0;
637 }
638 
sunxi_mmc_clk_set_rate(struct sunxi_mmc_host * host,struct mmc_ios * ios)639 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
640 				  struct mmc_ios *ios)
641 {
642 	u32 rate, oclk_dly, rval, sclk_dly;
643 	int ret;
644 
645 	rate = clk_round_rate(host->clk_mmc, ios->clock);
646 	dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %d\n",
647 		ios->clock, rate);
648 
649 	/* setting clock rate */
650 	ret = clk_set_rate(host->clk_mmc, rate);
651 	if (ret) {
652 		dev_err(mmc_dev(host->mmc), "error setting clk to %d: %d\n",
653 			rate, ret);
654 		return ret;
655 	}
656 
657 	ret = sunxi_mmc_oclk_onoff(host, 0);
658 	if (ret)
659 		return ret;
660 
661 	/* clear internal divider */
662 	rval = mmc_readl(host, REG_CLKCR);
663 	rval &= ~0xff;
664 	mmc_writel(host, REG_CLKCR, rval);
665 
666 	/* determine delays */
667 	if (rate <= 400000) {
668 		oclk_dly = host->clk_delays[SDXC_CLK_400K].output;
669 		sclk_dly = host->clk_delays[SDXC_CLK_400K].sample;
670 	} else if (rate <= 25000000) {
671 		oclk_dly = host->clk_delays[SDXC_CLK_25M].output;
672 		sclk_dly = host->clk_delays[SDXC_CLK_25M].sample;
673 	} else if (rate <= 50000000) {
674 		if (ios->timing == MMC_TIMING_UHS_DDR50) {
675 			oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].output;
676 			sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].sample;
677 		} else {
678 			oclk_dly = host->clk_delays[SDXC_CLK_50M].output;
679 			sclk_dly = host->clk_delays[SDXC_CLK_50M].sample;
680 		}
681 	} else {
682 		return -EINVAL;
683 	}
684 
685 	clk_set_phase(host->clk_sample, sclk_dly);
686 	clk_set_phase(host->clk_output, oclk_dly);
687 
688 	return sunxi_mmc_oclk_onoff(host, 1);
689 }
690 
sunxi_mmc_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)691 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
692 {
693 	struct sunxi_mmc_host *host = mmc_priv(mmc);
694 	u32 rval;
695 
696 	/* Set the power state */
697 	switch (ios->power_mode) {
698 	case MMC_POWER_ON:
699 		break;
700 
701 	case MMC_POWER_UP:
702 		mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
703 
704 		host->ferror = sunxi_mmc_init_host(mmc);
705 		if (host->ferror)
706 			return;
707 
708 		dev_dbg(mmc_dev(mmc), "power on!\n");
709 		break;
710 
711 	case MMC_POWER_OFF:
712 		dev_dbg(mmc_dev(mmc), "power off!\n");
713 		sunxi_mmc_reset_host(host);
714 		mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
715 		break;
716 	}
717 
718 	/* set bus width */
719 	switch (ios->bus_width) {
720 	case MMC_BUS_WIDTH_1:
721 		mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
722 		break;
723 	case MMC_BUS_WIDTH_4:
724 		mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
725 		break;
726 	case MMC_BUS_WIDTH_8:
727 		mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
728 		break;
729 	}
730 
731 	/* set ddr mode */
732 	rval = mmc_readl(host, REG_GCTRL);
733 	if (ios->timing == MMC_TIMING_UHS_DDR50)
734 		rval |= SDXC_DDR_MODE;
735 	else
736 		rval &= ~SDXC_DDR_MODE;
737 	mmc_writel(host, REG_GCTRL, rval);
738 
739 	/* set up clock */
740 	if (ios->clock && ios->power_mode) {
741 		host->ferror = sunxi_mmc_clk_set_rate(host, ios);
742 		/* Android code had a usleep_range(50000, 55000); here */
743 	}
744 }
745 
sunxi_mmc_enable_sdio_irq(struct mmc_host * mmc,int enable)746 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
747 {
748 	struct sunxi_mmc_host *host = mmc_priv(mmc);
749 	unsigned long flags;
750 	u32 imask;
751 
752 	spin_lock_irqsave(&host->lock, flags);
753 
754 	imask = mmc_readl(host, REG_IMASK);
755 	if (enable) {
756 		host->sdio_imask = SDXC_SDIO_INTERRUPT;
757 		imask |= SDXC_SDIO_INTERRUPT;
758 	} else {
759 		host->sdio_imask = 0;
760 		imask &= ~SDXC_SDIO_INTERRUPT;
761 	}
762 	mmc_writel(host, REG_IMASK, imask);
763 	spin_unlock_irqrestore(&host->lock, flags);
764 }
765 
sunxi_mmc_hw_reset(struct mmc_host * mmc)766 static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
767 {
768 	struct sunxi_mmc_host *host = mmc_priv(mmc);
769 	mmc_writel(host, REG_HWRST, 0);
770 	udelay(10);
771 	mmc_writel(host, REG_HWRST, 1);
772 	udelay(300);
773 }
774 
sunxi_mmc_request(struct mmc_host * mmc,struct mmc_request * mrq)775 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
776 {
777 	struct sunxi_mmc_host *host = mmc_priv(mmc);
778 	struct mmc_command *cmd = mrq->cmd;
779 	struct mmc_data *data = mrq->data;
780 	unsigned long iflags;
781 	u32 imask = SDXC_INTERRUPT_ERROR_BIT;
782 	u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
783 	bool wait_dma = host->wait_dma;
784 	int ret;
785 
786 	/* Check for set_ios errors (should never happen) */
787 	if (host->ferror) {
788 		mrq->cmd->error = host->ferror;
789 		mmc_request_done(mmc, mrq);
790 		return;
791 	}
792 
793 	if (data) {
794 		ret = sunxi_mmc_map_dma(host, data);
795 		if (ret < 0) {
796 			dev_err(mmc_dev(mmc), "map DMA failed\n");
797 			cmd->error = ret;
798 			data->error = ret;
799 			mmc_request_done(mmc, mrq);
800 			return;
801 		}
802 	}
803 
804 	if (cmd->opcode == MMC_GO_IDLE_STATE) {
805 		cmd_val |= SDXC_SEND_INIT_SEQUENCE;
806 		imask |= SDXC_COMMAND_DONE;
807 	}
808 
809 	if (cmd->flags & MMC_RSP_PRESENT) {
810 		cmd_val |= SDXC_RESP_EXPIRE;
811 		if (cmd->flags & MMC_RSP_136)
812 			cmd_val |= SDXC_LONG_RESPONSE;
813 		if (cmd->flags & MMC_RSP_CRC)
814 			cmd_val |= SDXC_CHECK_RESPONSE_CRC;
815 
816 		if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
817 			cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
818 			if (cmd->data->flags & MMC_DATA_STREAM) {
819 				imask |= SDXC_AUTO_COMMAND_DONE;
820 				cmd_val |= SDXC_SEQUENCE_MODE |
821 					   SDXC_SEND_AUTO_STOP;
822 			}
823 
824 			if (cmd->data->stop) {
825 				imask |= SDXC_AUTO_COMMAND_DONE;
826 				cmd_val |= SDXC_SEND_AUTO_STOP;
827 			} else {
828 				imask |= SDXC_DATA_OVER;
829 			}
830 
831 			if (cmd->data->flags & MMC_DATA_WRITE)
832 				cmd_val |= SDXC_WRITE;
833 			else
834 				wait_dma = true;
835 		} else {
836 			imask |= SDXC_COMMAND_DONE;
837 		}
838 	} else {
839 		imask |= SDXC_COMMAND_DONE;
840 	}
841 
842 	dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
843 		cmd_val & 0x3f, cmd_val, cmd->arg, imask,
844 		mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
845 
846 	spin_lock_irqsave(&host->lock, iflags);
847 
848 	if (host->mrq || host->manual_stop_mrq) {
849 		spin_unlock_irqrestore(&host->lock, iflags);
850 
851 		if (data)
852 			dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
853 				     sunxi_mmc_get_dma_dir(data));
854 
855 		dev_err(mmc_dev(mmc), "request already pending\n");
856 		mrq->cmd->error = -EBUSY;
857 		mmc_request_done(mmc, mrq);
858 		return;
859 	}
860 
861 	if (data) {
862 		mmc_writel(host, REG_BLKSZ, data->blksz);
863 		mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
864 		sunxi_mmc_start_dma(host, data);
865 	}
866 
867 	host->mrq = mrq;
868 	host->wait_dma = wait_dma;
869 	mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
870 	mmc_writel(host, REG_CARG, cmd->arg);
871 	mmc_writel(host, REG_CMDR, cmd_val);
872 
873 	spin_unlock_irqrestore(&host->lock, iflags);
874 }
875 
sunxi_mmc_card_busy(struct mmc_host * mmc)876 static int sunxi_mmc_card_busy(struct mmc_host *mmc)
877 {
878 	struct sunxi_mmc_host *host = mmc_priv(mmc);
879 
880 	return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
881 }
882 
883 static const struct of_device_id sunxi_mmc_of_match[] = {
884 	{ .compatible = "allwinner,sun4i-a10-mmc", },
885 	{ .compatible = "allwinner,sun5i-a13-mmc", },
886 	{ .compatible = "allwinner,sun9i-a80-mmc", },
887 	{ /* sentinel */ }
888 };
889 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
890 
891 static struct mmc_host_ops sunxi_mmc_ops = {
892 	.request	 = sunxi_mmc_request,
893 	.set_ios	 = sunxi_mmc_set_ios,
894 	.get_ro		 = mmc_gpio_get_ro,
895 	.get_cd		 = mmc_gpio_get_cd,
896 	.enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
897 	.hw_reset	 = sunxi_mmc_hw_reset,
898 	.card_busy	 = sunxi_mmc_card_busy,
899 };
900 
901 static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
902 	[SDXC_CLK_400K]		= { .output = 180, .sample = 180 },
903 	[SDXC_CLK_25M]		= { .output = 180, .sample =  75 },
904 	[SDXC_CLK_50M]		= { .output =  90, .sample = 120 },
905 	[SDXC_CLK_50M_DDR]	= { .output =  60, .sample = 120 },
906 };
907 
908 static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
909 	[SDXC_CLK_400K]		= { .output = 180, .sample = 180 },
910 	[SDXC_CLK_25M]		= { .output = 180, .sample =  75 },
911 	[SDXC_CLK_50M]		= { .output = 150, .sample = 120 },
912 	[SDXC_CLK_50M_DDR]	= { .output =  90, .sample = 120 },
913 };
914 
sunxi_mmc_resource_request(struct sunxi_mmc_host * host,struct platform_device * pdev)915 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
916 				      struct platform_device *pdev)
917 {
918 	struct device_node *np = pdev->dev.of_node;
919 	int ret;
920 
921 	if (of_device_is_compatible(np, "allwinner,sun4i-a10-mmc"))
922 		host->idma_des_size_bits = 13;
923 	else
924 		host->idma_des_size_bits = 16;
925 
926 	if (of_device_is_compatible(np, "allwinner,sun9i-a80-mmc"))
927 		host->clk_delays = sun9i_mmc_clk_delays;
928 	else
929 		host->clk_delays = sunxi_mmc_clk_delays;
930 
931 	ret = mmc_regulator_get_supply(host->mmc);
932 	if (ret) {
933 		if (ret != -EPROBE_DEFER)
934 			dev_err(&pdev->dev, "Could not get vmmc supply\n");
935 		return ret;
936 	}
937 
938 	host->reg_base = devm_ioremap_resource(&pdev->dev,
939 			      platform_get_resource(pdev, IORESOURCE_MEM, 0));
940 	if (IS_ERR(host->reg_base))
941 		return PTR_ERR(host->reg_base);
942 
943 	host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
944 	if (IS_ERR(host->clk_ahb)) {
945 		dev_err(&pdev->dev, "Could not get ahb clock\n");
946 		return PTR_ERR(host->clk_ahb);
947 	}
948 
949 	host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
950 	if (IS_ERR(host->clk_mmc)) {
951 		dev_err(&pdev->dev, "Could not get mmc clock\n");
952 		return PTR_ERR(host->clk_mmc);
953 	}
954 
955 	host->clk_output = devm_clk_get(&pdev->dev, "output");
956 	if (IS_ERR(host->clk_output)) {
957 		dev_err(&pdev->dev, "Could not get output clock\n");
958 		return PTR_ERR(host->clk_output);
959 	}
960 
961 	host->clk_sample = devm_clk_get(&pdev->dev, "sample");
962 	if (IS_ERR(host->clk_sample)) {
963 		dev_err(&pdev->dev, "Could not get sample clock\n");
964 		return PTR_ERR(host->clk_sample);
965 	}
966 
967 	host->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
968 	if (PTR_ERR(host->reset) == -EPROBE_DEFER)
969 		return PTR_ERR(host->reset);
970 
971 	ret = clk_prepare_enable(host->clk_ahb);
972 	if (ret) {
973 		dev_err(&pdev->dev, "Enable ahb clk err %d\n", ret);
974 		return ret;
975 	}
976 
977 	ret = clk_prepare_enable(host->clk_mmc);
978 	if (ret) {
979 		dev_err(&pdev->dev, "Enable mmc clk err %d\n", ret);
980 		goto error_disable_clk_ahb;
981 	}
982 
983 	ret = clk_prepare_enable(host->clk_output);
984 	if (ret) {
985 		dev_err(&pdev->dev, "Enable output clk err %d\n", ret);
986 		goto error_disable_clk_mmc;
987 	}
988 
989 	ret = clk_prepare_enable(host->clk_sample);
990 	if (ret) {
991 		dev_err(&pdev->dev, "Enable sample clk err %d\n", ret);
992 		goto error_disable_clk_output;
993 	}
994 
995 	if (!IS_ERR(host->reset)) {
996 		ret = reset_control_deassert(host->reset);
997 		if (ret) {
998 			dev_err(&pdev->dev, "reset err %d\n", ret);
999 			goto error_disable_clk_sample;
1000 		}
1001 	}
1002 
1003 	/*
1004 	 * Sometimes the controller asserts the irq on boot for some reason,
1005 	 * make sure the controller is in a sane state before enabling irqs.
1006 	 */
1007 	ret = sunxi_mmc_reset_host(host);
1008 	if (ret)
1009 		goto error_assert_reset;
1010 
1011 	host->irq = platform_get_irq(pdev, 0);
1012 	return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
1013 			sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
1014 
1015 error_assert_reset:
1016 	if (!IS_ERR(host->reset))
1017 		reset_control_assert(host->reset);
1018 error_disable_clk_sample:
1019 	clk_disable_unprepare(host->clk_sample);
1020 error_disable_clk_output:
1021 	clk_disable_unprepare(host->clk_output);
1022 error_disable_clk_mmc:
1023 	clk_disable_unprepare(host->clk_mmc);
1024 error_disable_clk_ahb:
1025 	clk_disable_unprepare(host->clk_ahb);
1026 	return ret;
1027 }
1028 
sunxi_mmc_probe(struct platform_device * pdev)1029 static int sunxi_mmc_probe(struct platform_device *pdev)
1030 {
1031 	struct sunxi_mmc_host *host;
1032 	struct mmc_host *mmc;
1033 	int ret;
1034 
1035 	mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
1036 	if (!mmc) {
1037 		dev_err(&pdev->dev, "mmc alloc host failed\n");
1038 		return -ENOMEM;
1039 	}
1040 
1041 	host = mmc_priv(mmc);
1042 	host->mmc = mmc;
1043 	spin_lock_init(&host->lock);
1044 
1045 	ret = sunxi_mmc_resource_request(host, pdev);
1046 	if (ret)
1047 		goto error_free_host;
1048 
1049 	host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1050 					  &host->sg_dma, GFP_KERNEL);
1051 	if (!host->sg_cpu) {
1052 		dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
1053 		ret = -ENOMEM;
1054 		goto error_free_host;
1055 	}
1056 
1057 	mmc->ops		= &sunxi_mmc_ops;
1058 	mmc->max_blk_count	= 8192;
1059 	mmc->max_blk_size	= 4096;
1060 	mmc->max_segs		= PAGE_SIZE / sizeof(struct sunxi_idma_des);
1061 	mmc->max_seg_size	= (1 << host->idma_des_size_bits);
1062 	mmc->max_req_size	= mmc->max_seg_size * mmc->max_segs;
1063 	/* 400kHz ~ 50MHz */
1064 	mmc->f_min		=   400000;
1065 	mmc->f_max		= 50000000;
1066 	mmc->caps	       |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1067 				  MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
1068 
1069 	ret = mmc_of_parse(mmc);
1070 	if (ret)
1071 		goto error_free_dma;
1072 
1073 	ret = mmc_add_host(mmc);
1074 	if (ret)
1075 		goto error_free_dma;
1076 
1077 	dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
1078 	platform_set_drvdata(pdev, mmc);
1079 	return 0;
1080 
1081 error_free_dma:
1082 	dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1083 error_free_host:
1084 	mmc_free_host(mmc);
1085 	return ret;
1086 }
1087 
sunxi_mmc_remove(struct platform_device * pdev)1088 static int sunxi_mmc_remove(struct platform_device *pdev)
1089 {
1090 	struct mmc_host	*mmc = platform_get_drvdata(pdev);
1091 	struct sunxi_mmc_host *host = mmc_priv(mmc);
1092 
1093 	mmc_remove_host(mmc);
1094 	disable_irq(host->irq);
1095 	sunxi_mmc_reset_host(host);
1096 
1097 	if (!IS_ERR(host->reset))
1098 		reset_control_assert(host->reset);
1099 
1100 	clk_disable_unprepare(host->clk_mmc);
1101 	clk_disable_unprepare(host->clk_ahb);
1102 
1103 	dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1104 	mmc_free_host(mmc);
1105 
1106 	return 0;
1107 }
1108 
1109 static struct platform_driver sunxi_mmc_driver = {
1110 	.driver = {
1111 		.name	= "sunxi-mmc",
1112 		.of_match_table = of_match_ptr(sunxi_mmc_of_match),
1113 	},
1114 	.probe		= sunxi_mmc_probe,
1115 	.remove		= sunxi_mmc_remove,
1116 };
1117 module_platform_driver(sunxi_mmc_driver);
1118 
1119 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
1120 MODULE_LICENSE("GPL v2");
1121 MODULE_AUTHOR("David Lanzend�rfer <david.lanzendoerfer@o2s.ch>");
1122 MODULE_ALIAS("platform:sunxi-mmc");
1123