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Searched refs:SET_BIT (Results 1 – 14 of 14) sorted by relevance

/drivers/video/fbdev/kyro/
DSTG4000VTG.c34 tmp |= SET_BIT(8); in DisableVGA()
43 tmp = (STG_READ_REG(DACSyncCtrl)) | SET_BIT(0) | SET_BIT(2); in StopVTG()
53 tmp = ((STG_READ_REG(DACSyncCtrl)) | SET_BIT(31)); in StartVTG()
157 tmp = STG_READ_REG(DACSyncCtrl) | SET_BIT(3) | SET_BIT(1); in SetupVTG()
DSTG4000Ramdac.c104 tmp &= ~SET_BIT(31); in InitialiseRamdac()
152 tmp = (STG_READ_REG(DACStreamCtrl)) & ~SET_BIT(0); in DisableRamdacOutput()
161 tmp = (STG_READ_REG(DACStreamCtrl)) | SET_BIT(0); in EnableRamdacOutput()
DSTG4000InitDevice.c299 tmp |= SET_BIT(14); in SetCoreClockPLL()
309 tmp |= SET_BIT(14); in SetCoreClockPLL()
317 tmp = ((STG_READ_REG(Thread0Enable)) | SET_BIT(0)); in SetCoreClockPLL()
321 tmp = ((STG_READ_REG(Thread1Enable)) | SET_BIT(0)); in SetCoreClockPLL()
DSTG4000OverlayDevice.c181 tmp |= SET_BIT(31); /* Overlay format to Planer */ in CreateOverlaySurface()
293 tmp |= SET_BIT(7); in EnableOverlayPlane()
298 tmp |= SET_BIT(1); /* video stream */ in EnableOverlayPlane()
DSTG4000Reg.h31 #define SET_BIT(n) (1<<(n)) macro
/drivers/usb/storage/
Drealtek_cr.c131 #define SET_BIT(data, idx) ((data) |= 1 << (idx)) macro
582 SET_BIT(value, 2); in config_autodelink_after_power_on()
587 SET_BIT(value, 7); in config_autodelink_after_power_on()
600 SET_BIT(value, 2); in config_autodelink_after_power_on()
647 SET_BIT(value, 2); in config_autodelink_before_power_down()
663 SET_BIT(value, 0); in config_autodelink_before_power_down()
665 SET_BIT(value, 2); in config_autodelink_before_power_down()
679 SET_BIT(value, 0); in config_autodelink_before_power_down()
680 SET_BIT(value, 7); in config_autodelink_before_power_down()
684 SET_BIT(value, 2); in config_autodelink_before_power_down()
/drivers/net/ethernet/apm/xgene/
Dxgene_enet_ring2.c31 ring_cfg[3] |= SET_BIT(X2_DEQINTEN); in xgene_enet_ring_init()
43 ring_cfg[5] |= SET_BIT(X2_QBASE_AM) | SET_BIT(X2_MSG_AM); in xgene_enet_ring_init()
Dxgene_enet_main.h209 #define SET_BIT(field) \ macro
Dxgene_enet_main.c86 SET_BIT(COHERENT)); in xgene_enet_refill_bufpool()
242 hopinfo |= SET_BIT(ET); in xgene_enet_work_msg()
255 SET_BIT(IC) | in xgene_enet_work_msg()
256 SET_BIT(TYPE_ETH_WORK_MESSAGE); in xgene_enet_work_msg()
327 SET_BIT(COHERENT)); in xgene_enet_setup_tx_desc()
/drivers/scsi/sym53c8xx_2/
Dsym_nvram.c248 #define SET_BIT 0 macro
261 case SET_BIT: in S24C16_set_bit()
285 S24C16_set_bit(np, 1, gpreg, SET_BIT); in S24C16_start()
297 S24C16_set_bit(np, 1, gpreg, SET_BIT); in S24C16_stop()
307 S24C16_set_bit(np, write_bit, gpreg, SET_BIT); in S24C16_do_bit()
501 #undef SET_BIT
/drivers/crypto/qat/qat_common/
Dqat_hal.c196 #define SET_BIT(wrd, bit) (wrd | 1 << bit) macro
212 SET_BIT(csr, CE_INUSE_CONTEXTS_BITPOS) : in qat_hal_set_ae_ctx_mode()
227 SET_BIT(csr, CE_NN_MODE_BITPOS) : in qat_hal_set_ae_nn_mode()
247 SET_BIT(csr, CE_LMADDR_0_GLOBAL_BITPOS) : in qat_hal_set_ae_lm_mode()
252 SET_BIT(csr, CE_LMADDR_1_GLOBAL_BITPOS) : in qat_hal_set_ae_lm_mode()
/drivers/staging/rts5208/
Drtsx_chip.h337 #define SET_BIT(data, idx) ((data) |= 1 << (idx)) macro
Drtsx_scsi.c432 SET_BIT(chip->lun_mc, lun); in test_unit_ready()
882 SET_BIT(chip->lun_mc, lun); in read_write()
1093 SET_BIT(chip->lun_mc, lun); in read_capacity()
Dsd.c4251 SET_BIT(chip->lun_mc, lun);