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Searched refs:SET_FIELD (Results 1 – 13 of 13) sorted by relevance

/drivers/net/ethernet/qlogic/qed/
Dqed_int.c442 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id); in qed_init_cau_sb_entry()
443 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number); in qed_init_cau_sb_entry()
444 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid); in qed_init_cau_sb_entry()
445 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F); in qed_init_cau_sb_entry()
446 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F); in qed_init_cau_sb_entry()
449 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, in qed_init_cau_sb_entry()
451 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, in qed_init_cau_sb_entry()
466 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state); in qed_init_cau_sb_entry()
467 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state); in qed_init_cau_sb_entry()
541 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset); in qed_int_cau_conf_pi()
[all …]
Dqed_hw.c284 SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1); in qed_fid_pretend()
285 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1); in qed_fid_pretend()
290 SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0); in qed_fid_pretend()
291 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0); in qed_fid_pretend()
292 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); in qed_fid_pretend()
312 SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id); in qed_port_pretend()
313 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1); in qed_port_pretend()
314 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); in qed_port_pretend()
329 SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0); in qed_port_unpretend()
330 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0); in qed_port_unpretend()
[all …]
Dqed_l2.c174 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1); in qed_sp_vport_start()
175 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1); in qed_sp_vport_start()
220 SET_FIELD(capabilities, in qed_sp_vport_update_rss()
223 SET_FIELD(capabilities, in qed_sp_vport_update_rss()
226 SET_FIELD(capabilities, in qed_sp_vport_update_rss()
229 SET_FIELD(capabilities, in qed_sp_vport_update_rss()
232 SET_FIELD(capabilities, in qed_sp_vport_update_rss()
235 SET_FIELD(capabilities, in qed_sp_vport_update_rss()
283 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, in qed_sp_update_accept_mode()
287 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED, in qed_sp_update_accept_mode()
[all …]
Dqed_init_fw_funcs.c105 value) SET_FIELD(var[cmd ## _ ## field ## \
361 SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_PQ_VALID, 1); in qed_tx_pq_map_rt_init()
362 SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_RL_VALID, in qed_tx_pq_map_rt_init()
364 SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VP_PQ_ID, first_tx_pq_id); in qed_tx_pq_map_rt_init()
365 SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_RL_ID, in qed_tx_pq_map_rt_init()
367 SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VOQ, voq); in qed_tx_pq_map_rt_init()
368 SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_WRR_WEIGHT_GROUP, in qed_tx_pq_map_rt_init()
Dqed_spq.c168 SET_FIELD(p_cxt->xstorm_ag_context.flags10, in qed_spq_hw_initialize()
170 SET_FIELD(p_cxt->xstorm_ag_context.flags1, in qed_spq_hw_initialize()
172 SET_FIELD(p_cxt->xstorm_ag_context.flags9, in qed_spq_hw_initialize()
212 SET_FIELD(db.params, CORE_DB_DATA_DEST, DB_DEST_XCM); in qed_spq_hw_post()
213 SET_FIELD(db.params, CORE_DB_DATA_AGG_CMD, DB_AGG_CMD_SET); in qed_spq_hw_post()
214 SET_FIELD(db.params, CORE_DB_DATA_AGG_VAL_SEL, in qed_spq_hw_post()
Dqed_cxt.c561 SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size); in qed_cdu_init_common()
562 SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste); in qed_cdu_init_common()
563 SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page); in qed_cdu_init_common()
688 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL); in qed_ilt_init_pf()
689 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR, in qed_ilt_init_pf()
/drivers/net/wireless/rt2x00/
Drt2x00reg.h246 #define SET_FIELD(__reg, __type, __field, __value)\ macro
263 SET_FIELD(__reg, struct rt2x00_field32, __field, __value)
268 SET_FIELD(__reg, struct rt2x00_field16, __field, __value)
273 SET_FIELD(__reg, struct rt2x00_field8, __field, __value)
/drivers/gpu/drm/gma500/
Dcdv_intel_display.c151 SET_FIELD(SB_OPCODE_READ, SB_OPCODE) | in cdv_sb_read()
152 SET_FIELD(SB_DEST_DPLL, SB_DEST) | in cdv_sb_read()
153 SET_FIELD(0xf, SB_BYTE_ENABLE)); in cdv_sb_read()
187 SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) | in cdv_sb_write()
188 SET_FIELD(SB_DEST_DPLL, SB_DEST) | in cdv_sb_write()
189 SET_FIELD(0xf, SB_BYTE_ENABLE)); in cdv_sb_write()
321 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER); in cdv_dpll_set_clock_cdv()
324 p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER); in cdv_dpll_set_clock_cdv()
327 p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER); in cdv_dpll_set_clock_cdv()
330 p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER); in cdv_dpll_set_clock_cdv()
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Dpsb_intel_reg.h1292 #define SET_FIELD(value, field) (((value) << field ## _SHIFT) & field ## _MASK) macro
/drivers/crypto/nx/
Dnx-842-powernv.c427 ccw = SET_FIELD(ccw, CCW_CT, nx842_ct); in nx842_powernv_function()
428 ccw = SET_FIELD(ccw, CCW_CI_842, 0); /* use 0 for hw auto-selection */ in nx842_powernv_function()
429 ccw = SET_FIELD(ccw, CCW_FC_842, fc); in nx842_powernv_function()
Dnx-842.h106 #define SET_FIELD(v, m, val) (((v) & ~(m)) | (((val) << MASK_LSH(m)) & (m))) macro
/drivers/net/ethernet/qlogic/qede/
Dqede_main.c2172 SET_FIELD(txq->tx_db.data.params, in qede_start_queues()
2174 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD, in qede_start_queues()
2176 SET_FIELD(txq->tx_db.data.params, in qede_start_queues()
/drivers/iommu/
Dmsm_iommu_hw-8xxx.h42 SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v))
44 SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v))
48 #define SET_FIELD(addr, mask, shift, v) \ macro