Searched refs:SKL_DPLL0 (Results 1 – 4 of 4) sorted by relevance
1119 pipe_config->ddi_pll_sel = SKL_DPLL0; in skl_edp_set_pll_config()1123 ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0); in skl_edp_set_pll_config()1127 SKL_DPLL0); in skl_edp_set_pll_config()1131 SKL_DPLL0); in skl_edp_set_pll_config()1135 SKL_DPLL0); in skl_edp_set_pll_config()1139 SKL_DPLL0); in skl_edp_set_pll_config()1146 SKL_DPLL0); in skl_edp_set_pll_config()1150 SKL_DPLL0); in skl_edp_set_pll_config()
5713 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | in skl_dpll0_enable()5714 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); in skl_dpll0_enable()5715 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); in skl_dpll0_enable()5718 SKL_DPLL0); in skl_dpll0_enable()5721 SKL_DPLL0); in skl_dpll0_enable()6715 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; in skylake_get_display_clock_speed()9762 pipe_config->ddi_pll_sel = SKL_DPLL0; in bxt_get_ddi_pll()9788 case SKL_DPLL0: in skylake_get_ddi_pll()
2307 WARN_ON(dpll != SKL_DPLL0); in intel_ddi_pre_enable()
417 #define SKL_DPLL0 0 macro