Searched refs:SOR_PLL0 (Results 1 – 2 of 2) sorted by relevance
| /drivers/gpu/drm/tegra/ |
| D | sor.c | 769 value = tegra_sor_readl(sor, SOR_PLL0); in tegra_sor_power_down()
771 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_power_down()
884 DUMP_REG(SOR_PLL0); in tegra_sor_show_regs()
1256 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_edp_enable()
1296 value = tegra_sor_readl(sor, SOR_PLL0); in tegra_sor_edp_enable()
1298 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_edp_enable()
1319 value = tegra_sor_readl(sor, SOR_PLL0); in tegra_sor_edp_enable()
1322 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_edp_enable()
1821 value = tegra_sor_readl(sor, SOR_PLL0); in tegra_sor_hdmi_enable()
1824 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_hdmi_enable()
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| D | sor.h | 86 #define SOR_PLL0 0x17 macro
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