Searched refs:SOR_PLL1 (Results 1 – 2 of 2) sorted by relevance
| /drivers/gpu/drm/tegra/ |
| D | sor.c | 343 value = tegra_sor_readl(sor, SOR_PLL1); in tegra_sor_dp_term_calibrate()
345 tegra_sor_writel(sor, value, SOR_PLL1); in tegra_sor_dp_term_calibrate()
350 value = tegra_sor_readl(sor, SOR_PLL1); in tegra_sor_dp_term_calibrate()
353 tegra_sor_writel(sor, value, SOR_PLL1); in tegra_sor_dp_term_calibrate()
357 value = tegra_sor_readl(sor, SOR_PLL1); in tegra_sor_dp_term_calibrate()
364 value = tegra_sor_readl(sor, SOR_PLL1); in tegra_sor_dp_term_calibrate()
367 tegra_sor_writel(sor, value, SOR_PLL1); in tegra_sor_dp_term_calibrate()
885 DUMP_REG(SOR_PLL1); in tegra_sor_show_regs()
1265 tegra_sor_writel(sor, value, SOR_PLL1); in tegra_sor_edp_enable()
1979 value = tegra_sor_readl(sor, SOR_PLL1); in tegra_sor_hdmi_enable()
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| D | sor.h | 103 #define SOR_PLL1 0x18 macro
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