Searched refs:SOR_PLL2 (Results 1 – 2 of 2) sorted by relevance
| /drivers/gpu/drm/tegra/ |
| D | sor.c | 763 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_power_down()
765 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_power_down()
773 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_power_down()
776 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_power_down()
886 DUMP_REG(SOR_PLL2); in tegra_sor_show_regs()
1245 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1247 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1258 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1262 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1268 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
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| D | sor.h | 112 #define SOR_PLL2 0x19 macro
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