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Searched refs:SOR_PLL2_SEQ_PLLCAPPD_ENFORCE (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/tegra/
Dsor.h114 #define SOR_PLL2_SEQ_PLLCAPPD_ENFORCE (1 << 24) macro
Dsor.c775 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_power_down()
1260 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_edp_enable()
1269 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0) in tegra_sor_edp_enable()
1292 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN | in tegra_sor_edp_enable()
1325 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_edp_enable()
1827 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_hdmi_enable()