Searched refs:SRC_MASK_FSYS (Results 1 – 6 of 6) sorted by relevance
| /drivers/clk/samsung/ |
| D | clk-exynos5410.c | 44 #define SRC_MASK_FSYS 0x10340 macro
148 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
150 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
152 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
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| D | clk-exynos5250.c | 56 #define SRC_MASK_FSYS 0x10340 macro
140 SRC_MASK_FSYS,
516 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
518 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
520 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
522 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
524 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
526 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
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| D | clk-exynos4.c | 65 #define SRC_MASK_FSYS 0xc340 macro
229 SRC_MASK_FSYS,
284 { .offset = SRC_MASK_FSYS, .value = 0x01011111, },
900 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,
902 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4,
904 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8,
906 GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12,
908 GATE(CLK_SCLK_MMC4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16,
1072 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
1113 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
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| D | clk-exynos5420.c | 79 #define SRC_MASK_FSYS 0x10340 macro
202 SRC_MASK_FSYS,
277 { .offset = SRC_MASK_FSYS, .value = 0x11111110, },
1033 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
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| D | clk-exynos4415.c | 68 #define SRC_MASK_FSYS 0xc340 macro
160 SRC_MASK_FSYS,
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| D | clk-exynos3250.c | 50 #define SRC_MASK_FSYS 0xc340 macro
134 SRC_MASK_FSYS,
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