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Searched refs:STEP_0_SPLL_REF_DIV (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/radeon/
Dr600_dpm.c487 STEP_0_SPLL_REF_DIV(divider), ~STEP_0_SPLL_REF_DIV_MASK); in r600_engine_clock_entry_set_reference_divider()
Dr600d.h1367 # define STEP_0_SPLL_REF_DIV(x) ((x) << 16) macro