1 /* 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2015 Intel Corporation. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * BSD LICENSE 20 * 21 * Copyright(c) 2015 Intel Corporation. 22 * 23 * Redistribution and use in source and binary forms, with or without 24 * modification, are permitted provided that the following conditions 25 * are met: 26 * 27 * - Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * - Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in 31 * the documentation and/or other materials provided with the 32 * distribution. 33 * - Neither the name of Intel Corporation nor the names of its 34 * contributors may be used to endorse or promote products derived 35 * from this software without specific prior written permission. 36 * 37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 48 * 49 */ 50 #ifndef __PLATFORM_CONFIG_H 51 #define __PLATFORM_CONFIG_H 52 53 #define METADATA_TABLE_FIELD_START_SHIFT 0 54 #define METADATA_TABLE_FIELD_START_LEN_BITS 15 55 #define METADATA_TABLE_FIELD_LEN_SHIFT 16 56 #define METADATA_TABLE_FIELD_LEN_LEN_BITS 16 57 58 /* Header structure */ 59 #define PLATFORM_CONFIG_HEADER_RECORD_IDX_SHIFT 0 60 #define PLATFORM_CONFIG_HEADER_RECORD_IDX_LEN_BITS 6 61 #define PLATFORM_CONFIG_HEADER_TABLE_LENGTH_SHIFT 16 62 #define PLATFORM_CONFIG_HEADER_TABLE_LENGTH_LEN_BITS 12 63 #define PLATFORM_CONFIG_HEADER_TABLE_TYPE_SHIFT 28 64 #define PLATFORM_CONFIG_HEADER_TABLE_TYPE_LEN_BITS 4 65 66 enum platform_config_table_type_encoding { 67 PLATFORM_CONFIG_TABLE_RESERVED, 68 PLATFORM_CONFIG_SYSTEM_TABLE, 69 PLATFORM_CONFIG_PORT_TABLE, 70 PLATFORM_CONFIG_RX_PRESET_TABLE, 71 PLATFORM_CONFIG_TX_PRESET_TABLE, 72 PLATFORM_CONFIG_QSFP_ATTEN_TABLE, 73 PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE, 74 PLATFORM_CONFIG_TABLE_MAX 75 }; 76 77 enum platform_config_system_table_fields { 78 SYSTEM_TABLE_RESERVED, 79 SYSTEM_TABLE_NODE_STRING, 80 SYSTEM_TABLE_SYSTEM_IMAGE_GUID, 81 SYSTEM_TABLE_NODE_GUID, 82 SYSTEM_TABLE_REVISION, 83 SYSTEM_TABLE_VENDOR_OUI, 84 SYSTEM_TABLE_META_VERSION, 85 SYSTEM_TABLE_DEVICE_ID, 86 SYSTEM_TABLE_PARTITION_ENFORCEMENT_CAP, 87 SYSTEM_TABLE_QSFP_POWER_CLASS_MAX, 88 SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_12G, 89 SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_25G, 90 SYSTEM_TABLE_VARIABLE_TABLE_ENTRIES_PER_PORT, 91 SYSTEM_TABLE_MAX 92 }; 93 94 enum platform_config_port_table_fields { 95 PORT_TABLE_RESERVED, 96 PORT_TABLE_PORT_TYPE, 97 PORT_TABLE_ATTENUATION_12G, 98 PORT_TABLE_ATTENUATION_25G, 99 PORT_TABLE_LINK_SPEED_SUPPORTED, 100 PORT_TABLE_LINK_WIDTH_SUPPORTED, 101 PORT_TABLE_VL_CAP, 102 PORT_TABLE_MTU_CAP, 103 PORT_TABLE_TX_LANE_ENABLE_MASK, 104 PORT_TABLE_LOCAL_MAX_TIMEOUT, 105 PORT_TABLE_AUTO_LANE_SHEDDING_ENABLED, 106 PORT_TABLE_EXTERNAL_LOOPBACK_ALLOWED, 107 PORT_TABLE_TX_PRESET_IDX_PASSIVE_CU, 108 PORT_TABLE_TX_PRESET_IDX_ACTIVE_NO_EQ, 109 PORT_TABLE_TX_PRESET_IDX_ACTIVE_EQ, 110 PORT_TABLE_RX_PRESET_IDX, 111 PORT_TABLE_CABLE_REACH_CLASS, 112 PORT_TABLE_MAX 113 }; 114 115 enum platform_config_rx_preset_table_fields { 116 RX_PRESET_TABLE_RESERVED, 117 RX_PRESET_TABLE_QSFP_RX_CDR_APPLY, 118 RX_PRESET_TABLE_QSFP_RX_EQ_APPLY, 119 RX_PRESET_TABLE_QSFP_RX_AMP_APPLY, 120 RX_PRESET_TABLE_QSFP_RX_CDR, 121 RX_PRESET_TABLE_QSFP_RX_EQ, 122 RX_PRESET_TABLE_QSFP_RX_AMP, 123 RX_PRESET_TABLE_MAX 124 }; 125 126 enum platform_config_tx_preset_table_fields { 127 TX_PRESET_TABLE_RESERVED, 128 TX_PRESET_TABLE_PRECUR, 129 TX_PRESET_TABLE_ATTN, 130 TX_PRESET_TABLE_POSTCUR, 131 TX_PRESET_TABLE_QSFP_TX_CDR_APPLY, 132 TX_PRESET_TABLE_QSFP_TX_EQ_APPLY, 133 TX_PRESET_TABLE_QSFP_TX_CDR, 134 TX_PRESET_TABLE_QSFP_TX_EQ, 135 TX_PRESET_TABLE_MAX 136 }; 137 138 enum platform_config_qsfp_attn_table_fields { 139 QSFP_ATTEN_TABLE_RESERVED, 140 QSFP_ATTEN_TABLE_TX_PRESET_IDX, 141 QSFP_ATTEN_TABLE_RX_PRESET_IDX, 142 QSFP_ATTEN_TABLE_MAX 143 }; 144 145 enum platform_config_variable_settings_table_fields { 146 VARIABLE_SETTINGS_TABLE_RESERVED, 147 VARIABLE_SETTINGS_TABLE_TX_PRESET_IDX, 148 VARIABLE_SETTINGS_TABLE_RX_PRESET_IDX, 149 VARIABLE_SETTINGS_TABLE_MAX 150 }; 151 152 struct platform_config_data { 153 u32 *table; 154 u32 *table_metadata; 155 u32 num_table; 156 }; 157 158 /* 159 * This struct acts as a quick reference into the platform_data binary image 160 * and is populated by parse_platform_config(...) depending on the specific 161 * META_VERSION 162 */ 163 struct platform_config_cache { 164 u8 cache_valid; 165 struct platform_config_data config_tables[PLATFORM_CONFIG_TABLE_MAX]; 166 }; 167 168 static const u32 platform_config_table_limits[PLATFORM_CONFIG_TABLE_MAX] = { 169 0, 170 SYSTEM_TABLE_MAX, 171 PORT_TABLE_MAX, 172 RX_PRESET_TABLE_MAX, 173 TX_PRESET_TABLE_MAX, 174 QSFP_ATTEN_TABLE_MAX, 175 VARIABLE_SETTINGS_TABLE_MAX 176 }; 177 178 /* This section defines default values and encodings for the 179 * fields defined for each table above 180 */ 181 182 /*===================================================== 183 * System table encodings 184 *====================================================*/ 185 #define PLATFORM_CONFIG_MAGIC_NUM 0x3d4f5041 186 #define PLATFORM_CONFIG_MAGIC_NUMBER_LEN 4 187 188 /* 189 * These power classes are the same as defined in SFF 8636 spec rev 2.4 190 * describing byte 129 in table 6-16, except enumerated in a different order 191 */ 192 enum platform_config_qsfp_power_class_encoding { 193 QSFP_POWER_CLASS_1 = 1, 194 QSFP_POWER_CLASS_2, 195 QSFP_POWER_CLASS_3, 196 QSFP_POWER_CLASS_4, 197 QSFP_POWER_CLASS_5, 198 QSFP_POWER_CLASS_6, 199 QSFP_POWER_CLASS_7 200 }; 201 202 203 /*===================================================== 204 * Port table encodings 205 *==================================================== */ 206 enum platform_config_port_type_encoding { 207 PORT_TYPE_RESERVED, 208 PORT_TYPE_DISCONNECTED, 209 PORT_TYPE_FIXED, 210 PORT_TYPE_VARIABLE, 211 PORT_TYPE_QSFP, 212 PORT_TYPE_MAX 213 }; 214 215 enum platform_config_link_speed_supported_encoding { 216 LINK_SPEED_SUPP_12G = 1, 217 LINK_SPEED_SUPP_25G, 218 LINK_SPEED_SUPP_12G_25G, 219 LINK_SPEED_SUPP_MAX 220 }; 221 222 /* 223 * This is a subset (not strict) of the link downgrades 224 * supported. The link downgrades supported are expected 225 * to be supplied to the driver by another entity such as 226 * the fabric manager 227 */ 228 enum platform_config_link_width_supported_encoding { 229 LINK_WIDTH_SUPP_1X = 1, 230 LINK_WIDTH_SUPP_2X, 231 LINK_WIDTH_SUPP_2X_1X, 232 LINK_WIDTH_SUPP_3X, 233 LINK_WIDTH_SUPP_3X_1X, 234 LINK_WIDTH_SUPP_3X_2X, 235 LINK_WIDTH_SUPP_3X_2X_1X, 236 LINK_WIDTH_SUPP_4X, 237 LINK_WIDTH_SUPP_4X_1X, 238 LINK_WIDTH_SUPP_4X_2X, 239 LINK_WIDTH_SUPP_4X_2X_1X, 240 LINK_WIDTH_SUPP_4X_3X, 241 LINK_WIDTH_SUPP_4X_3X_1X, 242 LINK_WIDTH_SUPP_4X_3X_2X, 243 LINK_WIDTH_SUPP_4X_3X_2X_1X, 244 LINK_WIDTH_SUPP_MAX 245 }; 246 247 enum platform_config_virtual_lane_capability_encoding { 248 VL_CAP_VL0 = 1, 249 VL_CAP_VL0_1, 250 VL_CAP_VL0_2, 251 VL_CAP_VL0_3, 252 VL_CAP_VL0_4, 253 VL_CAP_VL0_5, 254 VL_CAP_VL0_6, 255 VL_CAP_VL0_7, 256 VL_CAP_VL0_8, 257 VL_CAP_VL0_9, 258 VL_CAP_VL0_10, 259 VL_CAP_VL0_11, 260 VL_CAP_VL0_12, 261 VL_CAP_VL0_13, 262 VL_CAP_VL0_14, 263 VL_CAP_MAX 264 }; 265 266 /* Max MTU */ 267 enum platform_config_mtu_capability_encoding { 268 MTU_CAP_256 = 1, 269 MTU_CAP_512 = 2, 270 MTU_CAP_1024 = 3, 271 MTU_CAP_2048 = 4, 272 MTU_CAP_4096 = 5, 273 MTU_CAP_8192 = 6, 274 MTU_CAP_10240 = 7 275 }; 276 277 enum platform_config_local_max_timeout_encoding { 278 LOCAL_MAX_TIMEOUT_10_MS = 1, 279 LOCAL_MAX_TIMEOUT_100_MS, 280 LOCAL_MAX_TIMEOUT_1_S, 281 LOCAL_MAX_TIMEOUT_10_S, 282 LOCAL_MAX_TIMEOUT_100_S, 283 LOCAL_MAX_TIMEOUT_1000_S 284 }; 285 286 #endif /*__PLATFORM_CONFIG_H*/ 287