1 /*
2 * Definitions for Xilinx Axi Ethernet device driver.
3 *
4 * Copyright (c) 2009 Secret Lab Technologies, Ltd.
5 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
6 */
7
8 #ifndef XILINX_AXIENET_H
9 #define XILINX_AXIENET_H
10
11 #include <linux/netdevice.h>
12 #include <linux/spinlock.h>
13 #include <linux/interrupt.h>
14 #include <linux/if_vlan.h>
15
16 /* Packet size info */
17 #define XAE_HDR_SIZE 14 /* Size of Ethernet header */
18 #define XAE_TRL_SIZE 4 /* Size of Ethernet trailer (FCS) */
19 #define XAE_MTU 1500 /* Max MTU of an Ethernet frame */
20 #define XAE_JUMBO_MTU 9000 /* Max MTU of a jumbo Eth. frame */
21
22 #define XAE_MAX_FRAME_SIZE (XAE_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE)
23 #define XAE_MAX_VLAN_FRAME_SIZE (XAE_MTU + VLAN_ETH_HLEN + XAE_TRL_SIZE)
24 #define XAE_MAX_JUMBO_FRAME_SIZE (XAE_JUMBO_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE)
25
26 /* Configuration options */
27
28 /* Accept all incoming packets. Default: disabled (cleared) */
29 #define XAE_OPTION_PROMISC (1 << 0)
30
31 /* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */
32 #define XAE_OPTION_JUMBO (1 << 1)
33
34 /* VLAN Rx & Tx frame support. Default: disabled (cleared) */
35 #define XAE_OPTION_VLAN (1 << 2)
36
37 /* Enable recognition of flow control frames on Rx. Default: enabled (set) */
38 #define XAE_OPTION_FLOW_CONTROL (1 << 4)
39
40 /* Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
41 * stripped. Default: disabled (set)
42 */
43 #define XAE_OPTION_FCS_STRIP (1 << 5)
44
45 /* Generate FCS field and add PAD automatically for outgoing frames.
46 * Default: enabled (set)
47 */
48 #define XAE_OPTION_FCS_INSERT (1 << 6)
49
50 /* Enable Length/Type error checking for incoming frames. When this option is
51 * set, the MAC will filter frames that have a mismatched type/length field
52 * and if XAE_OPTION_REPORT_RXERR is set, the user is notified when these
53 * types of frames are encountered. When this option is cleared, the MAC will
54 * allow these types of frames to be received. Default: enabled (set)
55 */
56 #define XAE_OPTION_LENTYPE_ERR (1 << 7)
57
58 /* Enable the transmitter. Default: enabled (set) */
59 #define XAE_OPTION_TXEN (1 << 11)
60
61 /* Enable the receiver. Default: enabled (set) */
62 #define XAE_OPTION_RXEN (1 << 12)
63
64 /* Default options set when device is initialized or reset */
65 #define XAE_OPTION_DEFAULTS \
66 (XAE_OPTION_TXEN | \
67 XAE_OPTION_FLOW_CONTROL | \
68 XAE_OPTION_RXEN)
69
70 /* Axi DMA Register definitions */
71
72 #define XAXIDMA_TX_CR_OFFSET 0x00000000 /* Channel control */
73 #define XAXIDMA_TX_SR_OFFSET 0x00000004 /* Status */
74 #define XAXIDMA_TX_CDESC_OFFSET 0x00000008 /* Current descriptor pointer */
75 #define XAXIDMA_TX_TDESC_OFFSET 0x00000010 /* Tail descriptor pointer */
76
77 #define XAXIDMA_RX_CR_OFFSET 0x00000030 /* Channel control */
78 #define XAXIDMA_RX_SR_OFFSET 0x00000034 /* Status */
79 #define XAXIDMA_RX_CDESC_OFFSET 0x00000038 /* Current descriptor pointer */
80 #define XAXIDMA_RX_TDESC_OFFSET 0x00000040 /* Tail descriptor pointer */
81
82 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
83 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
84
85 #define XAXIDMA_BD_NDESC_OFFSET 0x00 /* Next descriptor pointer */
86 #define XAXIDMA_BD_BUFA_OFFSET 0x08 /* Buffer address */
87 #define XAXIDMA_BD_CTRL_LEN_OFFSET 0x18 /* Control/buffer length */
88 #define XAXIDMA_BD_STS_OFFSET 0x1C /* Status */
89 #define XAXIDMA_BD_USR0_OFFSET 0x20 /* User IP specific word0 */
90 #define XAXIDMA_BD_USR1_OFFSET 0x24 /* User IP specific word1 */
91 #define XAXIDMA_BD_USR2_OFFSET 0x28 /* User IP specific word2 */
92 #define XAXIDMA_BD_USR3_OFFSET 0x2C /* User IP specific word3 */
93 #define XAXIDMA_BD_USR4_OFFSET 0x30 /* User IP specific word4 */
94 #define XAXIDMA_BD_ID_OFFSET 0x34 /* Sw ID */
95 #define XAXIDMA_BD_HAS_STSCNTRL_OFFSET 0x38 /* Whether has stscntrl strm */
96 #define XAXIDMA_BD_HAS_DRE_OFFSET 0x3C /* Whether has DRE */
97
98 #define XAXIDMA_BD_HAS_DRE_SHIFT 8 /* Whether has DRE shift */
99 #define XAXIDMA_BD_HAS_DRE_MASK 0xF00 /* Whether has DRE mask */
100 #define XAXIDMA_BD_WORDLEN_MASK 0xFF /* Whether has DRE mask */
101
102 #define XAXIDMA_BD_CTRL_LENGTH_MASK 0x007FFFFF /* Requested len */
103 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
104 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
105 #define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */
106
107 #define XAXIDMA_DELAY_MASK 0xFF000000 /* Delay timeout counter */
108 #define XAXIDMA_COALESCE_MASK 0x00FF0000 /* Coalesce counter */
109
110 #define XAXIDMA_DELAY_SHIFT 24
111 #define XAXIDMA_COALESCE_SHIFT 16
112
113 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
114 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
115 #define XAXIDMA_IRQ_ERROR_MASK 0x00004000 /* Error interrupt */
116 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
117
118 /* Default TX/RX Threshold and waitbound values for SGDMA mode */
119 #define XAXIDMA_DFT_TX_THRESHOLD 24
120 #define XAXIDMA_DFT_TX_WAITBOUND 254
121 #define XAXIDMA_DFT_RX_THRESHOLD 24
122 #define XAXIDMA_DFT_RX_WAITBOUND 254
123
124 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
125 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
126 #define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */
127
128 #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
129 #define XAXIDMA_BD_STS_COMPLETE_MASK 0x80000000 /* Completed */
130 #define XAXIDMA_BD_STS_DEC_ERR_MASK 0x40000000 /* Decode error */
131 #define XAXIDMA_BD_STS_SLV_ERR_MASK 0x20000000 /* Slave error */
132 #define XAXIDMA_BD_STS_INT_ERR_MASK 0x10000000 /* Internal err */
133 #define XAXIDMA_BD_STS_ALL_ERR_MASK 0x70000000 /* All errors */
134 #define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /* First rx pkt */
135 #define XAXIDMA_BD_STS_RXEOF_MASK 0x04000000 /* Last rx pkt */
136 #define XAXIDMA_BD_STS_ALL_MASK 0xFC000000 /* All status bits */
137
138 #define XAXIDMA_BD_MINIMUM_ALIGNMENT 0x40
139
140 /* Axi Ethernet registers definition */
141 #define XAE_RAF_OFFSET 0x00000000 /* Reset and Address filter */
142 #define XAE_TPF_OFFSET 0x00000004 /* Tx Pause Frame */
143 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
144 #define XAE_IS_OFFSET 0x0000000C /* Interrupt status */
145 #define XAE_IP_OFFSET 0x00000010 /* Interrupt pending */
146 #define XAE_IE_OFFSET 0x00000014 /* Interrupt enable */
147 #define XAE_TTAG_OFFSET 0x00000018 /* Tx VLAN TAG */
148 #define XAE_RTAG_OFFSET 0x0000001C /* Rx VLAN TAG */
149 #define XAE_UAWL_OFFSET 0x00000020 /* Unicast address word lower */
150 #define XAE_UAWU_OFFSET 0x00000024 /* Unicast address word upper */
151 #define XAE_TPID0_OFFSET 0x00000028 /* VLAN TPID0 register */
152 #define XAE_TPID1_OFFSET 0x0000002C /* VLAN TPID1 register */
153 #define XAE_PPST_OFFSET 0x00000030 /* PCS PMA Soft Temac Status Reg */
154 #define XAE_RCW0_OFFSET 0x00000400 /* Rx Configuration Word 0 */
155 #define XAE_RCW1_OFFSET 0x00000404 /* Rx Configuration Word 1 */
156 #define XAE_TC_OFFSET 0x00000408 /* Tx Configuration */
157 #define XAE_FCC_OFFSET 0x0000040C /* Flow Control Configuration */
158 #define XAE_EMMC_OFFSET 0x00000410 /* EMAC mode configuration */
159 #define XAE_PHYC_OFFSET 0x00000414 /* RGMII/SGMII configuration */
160 #define XAE_MDIO_MC_OFFSET 0x00000500 /* MII Management Config */
161 #define XAE_MDIO_MCR_OFFSET 0x00000504 /* MII Management Control */
162 #define XAE_MDIO_MWD_OFFSET 0x00000508 /* MII Management Write Data */
163 #define XAE_MDIO_MRD_OFFSET 0x0000050C /* MII Management Read Data */
164 #define XAE_MDIO_MIS_OFFSET 0x00000600 /* MII Management Interrupt Status */
165 /* MII Mgmt Interrupt Pending register offset */
166 #define XAE_MDIO_MIP_OFFSET 0x00000620
167 /* MII Management Interrupt Enable register offset */
168 #define XAE_MDIO_MIE_OFFSET 0x00000640
169 /* MII Management Interrupt Clear register offset. */
170 #define XAE_MDIO_MIC_OFFSET 0x00000660
171 #define XAE_UAW0_OFFSET 0x00000700 /* Unicast address word 0 */
172 #define XAE_UAW1_OFFSET 0x00000704 /* Unicast address word 1 */
173 #define XAE_FMI_OFFSET 0x00000708 /* Filter Mask Index */
174 #define XAE_AF0_OFFSET 0x00000710 /* Address Filter 0 */
175 #define XAE_AF1_OFFSET 0x00000714 /* Address Filter 1 */
176
177 #define XAE_TX_VLAN_DATA_OFFSET 0x00004000 /* TX VLAN data table address */
178 #define XAE_RX_VLAN_DATA_OFFSET 0x00008000 /* RX VLAN data table address */
179 #define XAE_MCAST_TABLE_OFFSET 0x00020000 /* Multicast table address */
180
181 /* Bit Masks for Axi Ethernet RAF register */
182 /* Reject receive multicast destination address */
183 #define XAE_RAF_MCSTREJ_MASK 0x00000002
184 /* Reject receive broadcast destination address */
185 #define XAE_RAF_BCSTREJ_MASK 0x00000004
186 #define XAE_RAF_TXVTAGMODE_MASK 0x00000018 /* Tx VLAN TAG mode */
187 #define XAE_RAF_RXVTAGMODE_MASK 0x00000060 /* Rx VLAN TAG mode */
188 #define XAE_RAF_TXVSTRPMODE_MASK 0x00000180 /* Tx VLAN STRIP mode */
189 #define XAE_RAF_RXVSTRPMODE_MASK 0x00000600 /* Rx VLAN STRIP mode */
190 #define XAE_RAF_NEWFNCENBL_MASK 0x00000800 /* New function mode */
191 /* Exteneded Multicast Filtering mode */
192 #define XAE_RAF_EMULTIFLTRENBL_MASK 0x00001000
193 #define XAE_RAF_STATSRST_MASK 0x00002000 /* Stats. Counter Reset */
194 #define XAE_RAF_RXBADFRMEN_MASK 0x00004000 /* Recv Bad Frame Enable */
195 #define XAE_RAF_TXVTAGMODE_SHIFT 3 /* Tx Tag mode shift bits */
196 #define XAE_RAF_RXVTAGMODE_SHIFT 5 /* Rx Tag mode shift bits */
197 #define XAE_RAF_TXVSTRPMODE_SHIFT 7 /* Tx strip mode shift bits*/
198 #define XAE_RAF_RXVSTRPMODE_SHIFT 9 /* Rx Strip mode shift bits*/
199
200 /* Bit Masks for Axi Ethernet TPF and IFGP registers */
201 #define XAE_TPF_TPFV_MASK 0x0000FFFF /* Tx pause frame value */
202 /* Transmit inter-frame gap adjustment value */
203 #define XAE_IFGP0_IFGP_MASK 0x0000007F
204
205 /* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
206 * for all 3 registers.
207 */
208 /* Hard register access complete */
209 #define XAE_INT_HARDACSCMPLT_MASK 0x00000001
210 /* Auto negotiation complete */
211 #define XAE_INT_AUTONEG_MASK 0x00000002
212 #define XAE_INT_RXCMPIT_MASK 0x00000004 /* Rx complete */
213 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
214 #define XAE_INT_RXFIFOOVR_MASK 0x00000010 /* Rx fifo overrun */
215 #define XAE_INT_TXCMPIT_MASK 0x00000020 /* Tx complete */
216 #define XAE_INT_RXDCMLOCK_MASK 0x00000040 /* Rx Dcm Lock */
217 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
218 #define XAE_INT_PHYRSTCMPLT_MASK 0x00000100 /* Phy Reset complete */
219 #define XAE_INT_ALL_MASK 0x0000003F /* All the ints */
220
221 /* INT bits that indicate receive errors */
222 #define XAE_INT_RECV_ERROR_MASK \
223 (XAE_INT_RXRJECT_MASK | XAE_INT_RXFIFOOVR_MASK)
224
225 /* Bit masks for Axi Ethernet VLAN TPID Word 0 register */
226 #define XAE_TPID_0_MASK 0x0000FFFF /* TPID 0 */
227 #define XAE_TPID_1_MASK 0xFFFF0000 /* TPID 1 */
228
229 /* Bit masks for Axi Ethernet VLAN TPID Word 1 register */
230 #define XAE_TPID_2_MASK 0x0000FFFF /* TPID 0 */
231 #define XAE_TPID_3_MASK 0xFFFF0000 /* TPID 1 */
232
233 /* Bit masks for Axi Ethernet RCW1 register */
234 #define XAE_RCW1_RST_MASK 0x80000000 /* Reset */
235 #define XAE_RCW1_JUM_MASK 0x40000000 /* Jumbo frame enable */
236 /* In-Band FCS enable (FCS not stripped) */
237 #define XAE_RCW1_FCS_MASK 0x20000000
238 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
239 #define XAE_RCW1_VLAN_MASK 0x08000000 /* VLAN frame enable */
240 /* Length/type field valid check disable */
241 #define XAE_RCW1_LT_DIS_MASK 0x02000000
242 /* Control frame Length check disable */
243 #define XAE_RCW1_CL_DIS_MASK 0x01000000
244 /* Pause frame source address bits [47:32]. Bits [31:0] are
245 * stored in register RCW0
246 */
247 #define XAE_RCW1_PAUSEADDR_MASK 0x0000FFFF
248
249 /* Bit masks for Axi Ethernet TC register */
250 #define XAE_TC_RST_MASK 0x80000000 /* Reset */
251 #define XAE_TC_JUM_MASK 0x40000000 /* Jumbo frame enable */
252 /* In-Band FCS enable (FCS not generated) */
253 #define XAE_TC_FCS_MASK 0x20000000
254 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
255 #define XAE_TC_VLAN_MASK 0x08000000 /* VLAN frame enable */
256 /* Inter-frame gap adjustment enable */
257 #define XAE_TC_IFG_MASK 0x02000000
258
259 /* Bit masks for Axi Ethernet FCC register */
260 #define XAE_FCC_FCRX_MASK 0x20000000 /* Rx flow control enable */
261 #define XAE_FCC_FCTX_MASK 0x40000000 /* Tx flow control enable */
262
263 /* Bit masks for Axi Ethernet EMMC register */
264 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
265 #define XAE_EMMC_RGMII_MASK 0x20000000 /* RGMII mode enable */
266 #define XAE_EMMC_SGMII_MASK 0x10000000 /* SGMII mode enable */
267 #define XAE_EMMC_GPCS_MASK 0x08000000 /* 1000BaseX mode enable */
268 #define XAE_EMMC_HOST_MASK 0x04000000 /* Host interface enable */
269 #define XAE_EMMC_TX16BIT 0x02000000 /* 16 bit Tx client enable */
270 #define XAE_EMMC_RX16BIT 0x01000000 /* 16 bit Rx client enable */
271 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
272 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
273 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
274
275 /* Bit masks for Axi Ethernet PHYC register */
276 #define XAE_PHYC_SGMIILINKSPEED_MASK 0xC0000000 /* SGMII link speed mask*/
277 #define XAE_PHYC_RGMIILINKSPEED_MASK 0x0000000C /* RGMII link speed */
278 #define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */
279 #define XAE_PHYC_RGMIILINK_MASK 0x00000001 /* RGMII link status */
280 #define XAE_PHYC_RGLINKSPD_10 0x00000000 /* RGMII link 10 Mbit */
281 #define XAE_PHYC_RGLINKSPD_100 0x00000004 /* RGMII link 100 Mbit */
282 #define XAE_PHYC_RGLINKSPD_1000 0x00000008 /* RGMII link 1000 Mbit */
283 #define XAE_PHYC_SGLINKSPD_10 0x00000000 /* SGMII link 10 Mbit */
284 #define XAE_PHYC_SGLINKSPD_100 0x40000000 /* SGMII link 100 Mbit */
285 #define XAE_PHYC_SGLINKSPD_1000 0x80000000 /* SGMII link 1000 Mbit */
286
287 /* Bit masks for Axi Ethernet MDIO interface MC register */
288 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable */
289 #define XAE_MDIO_MC_CLOCK_DIVIDE_MAX 0x3F /* Maximum MDIO divisor */
290
291 /* Bit masks for Axi Ethernet MDIO interface MCR register */
292 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
293 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
294 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
295 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
296 #define XAE_MDIO_MCR_OP_MASK 0x0000C000 /* Operation Code Mask */
297 #define XAE_MDIO_MCR_OP_SHIFT 13 /* Operation Code Shift */
298 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
299 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
300 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
301 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
302
303 /* Bit masks for Axi Ethernet MDIO interface MIS, MIP, MIE, MIC registers */
304 #define XAE_MDIO_INT_MIIM_RDY_MASK 0x00000001 /* MIIM Interrupt */
305
306 /* Bit masks for Axi Ethernet UAW1 register */
307 /* Station address bits [47:32]; Station address
308 * bits [31:0] are stored in register UAW0
309 */
310 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
311
312 /* Bit masks for Axi Ethernet FMI register */
313 #define XAE_FMI_PM_MASK 0x80000000 /* Promis. mode enable */
314 #define XAE_FMI_IND_MASK 0x00000003 /* Index Mask */
315
316 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
317
318 /* Defines for different options for C_PHY_TYPE parameter in Axi Ethernet IP */
319 #define XAE_PHY_TYPE_MII 0
320 #define XAE_PHY_TYPE_GMII 1
321 #define XAE_PHY_TYPE_RGMII_1_3 2
322 #define XAE_PHY_TYPE_RGMII_2_0 3
323 #define XAE_PHY_TYPE_SGMII 4
324 #define XAE_PHY_TYPE_1000BASE_X 5
325
326 /* Total number of entries in the hardware multicast table. */
327 #define XAE_MULTICAST_CAM_TABLE_NUM 4
328
329 /* Axi Ethernet Synthesis features */
330 #define XAE_FEATURE_PARTIAL_RX_CSUM (1 << 0)
331 #define XAE_FEATURE_PARTIAL_TX_CSUM (1 << 1)
332 #define XAE_FEATURE_FULL_RX_CSUM (1 << 2)
333 #define XAE_FEATURE_FULL_TX_CSUM (1 << 3)
334
335 #define XAE_NO_CSUM_OFFLOAD 0
336
337 #define XAE_FULL_CSUM_STATUS_MASK 0x00000038
338 #define XAE_IP_UDP_CSUM_VALIDATED 0x00000003
339 #define XAE_IP_TCP_CSUM_VALIDATED 0x00000002
340
341 #define DELAY_OF_ONE_MILLISEC 1000
342
343 /**
344 * struct axidma_bd - Axi Dma buffer descriptor layout
345 * @next: MM2S/S2MM Next Descriptor Pointer
346 * @reserved1: Reserved and not used
347 * @phys: MM2S/S2MM Buffer Address
348 * @reserved2: Reserved and not used
349 * @reserved3: Reserved and not used
350 * @reserved4: Reserved and not used
351 * @cntrl: MM2S/S2MM Control value
352 * @status: MM2S/S2MM Status value
353 * @app0: MM2S/S2MM User Application Field 0.
354 * @app1: MM2S/S2MM User Application Field 1.
355 * @app2: MM2S/S2MM User Application Field 2.
356 * @app3: MM2S/S2MM User Application Field 3.
357 * @app4: MM2S/S2MM User Application Field 4.
358 * @sw_id_offset: MM2S/S2MM Sw ID
359 * @reserved5: Reserved and not used
360 * @reserved6: Reserved and not used
361 */
362 struct axidma_bd {
363 u32 next; /* Physical address of next buffer descriptor */
364 u32 reserved1;
365 u32 phys;
366 u32 reserved2;
367 u32 reserved3;
368 u32 reserved4;
369 u32 cntrl;
370 u32 status;
371 u32 app0;
372 u32 app1; /* TX start << 16 | insert */
373 u32 app2; /* TX csum seed */
374 u32 app3;
375 u32 app4;
376 u32 sw_id_offset;
377 u32 reserved5;
378 u32 reserved6;
379 };
380
381 /**
382 * struct axienet_local - axienet private per device data
383 * @ndev: Pointer for net_device to which it will be attached.
384 * @dev: Pointer to device structure
385 * @phy_dev: Pointer to PHY device structure attached to the axienet_local
386 * @phy_node: Pointer to device node structure
387 * @mii_bus: Pointer to MII bus structure
388 * @mdio_irqs: IRQs table for MDIO bus required in mii_bus structure
389 * @regs: Base address for the axienet_local device address space
390 * @dma_regs: Base address for the axidma device address space
391 * @dma_err_tasklet: Tasklet structure to process Axi DMA errors
392 * @tx_irq: Axidma TX IRQ number
393 * @rx_irq: Axidma RX IRQ number
394 * @phy_type: Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
395 * @options: AxiEthernet option word
396 * @last_link: Phy link state in which the PHY was negotiated earlier
397 * @features: Stores the extended features supported by the axienet hw
398 * @tx_bd_v: Virtual address of the TX buffer descriptor ring
399 * @tx_bd_p: Physical address(start address) of the TX buffer descr. ring
400 * @rx_bd_v: Virtual address of the RX buffer descriptor ring
401 * @rx_bd_p: Physical address(start address) of the RX buffer descr. ring
402 * @tx_bd_ci: Stores the index of the Tx buffer descriptor in the ring being
403 * accessed currently. Used while alloc. BDs before a TX starts
404 * @tx_bd_tail: Stores the index of the Tx buffer descriptor in the ring being
405 * accessed currently. Used while processing BDs after the TX
406 * completed.
407 * @rx_bd_ci: Stores the index of the Rx buffer descriptor in the ring being
408 * accessed currently.
409 * @max_frm_size: Stores the maximum size of the frame that can be that
410 * Txed/Rxed in the existing hardware. If jumbo option is
411 * supported, the maximum frame size would be 9k. Else it is
412 * 1522 bytes (assuming support for basic VLAN)
413 * @rxmem: Stores rx memory size for jumbo frame handling.
414 * @csum_offload_on_tx_path: Stores the checksum selection on TX side.
415 * @csum_offload_on_rx_path: Stores the checksum selection on RX side.
416 * @coalesce_count_rx: Store the irq coalesce on RX side.
417 * @coalesce_count_tx: Store the irq coalesce on TX side.
418 */
419 struct axienet_local {
420 struct net_device *ndev;
421 struct device *dev;
422
423 /* Connection to PHY device */
424 struct phy_device *phy_dev; /* Pointer to PHY device */
425 struct device_node *phy_node;
426
427 /* MDIO bus data */
428 struct mii_bus *mii_bus; /* MII bus reference */
429 int mdio_irqs[PHY_MAX_ADDR]; /* IRQs table for MDIO bus */
430
431 /* IO registers, dma functions and IRQs */
432 void __iomem *regs;
433 void __iomem *dma_regs;
434
435 struct tasklet_struct dma_err_tasklet;
436
437 int tx_irq;
438 int rx_irq;
439 u32 phy_type;
440
441 u32 options; /* Current options word */
442 u32 last_link;
443 u32 features;
444
445 /* Buffer descriptors */
446 struct axidma_bd *tx_bd_v;
447 dma_addr_t tx_bd_p;
448 struct axidma_bd *rx_bd_v;
449 dma_addr_t rx_bd_p;
450 u32 tx_bd_ci;
451 u32 tx_bd_tail;
452 u32 rx_bd_ci;
453
454 u32 max_frm_size;
455 u32 rxmem;
456
457 int csum_offload_on_tx_path;
458 int csum_offload_on_rx_path;
459
460 u32 coalesce_count_rx;
461 u32 coalesce_count_tx;
462 };
463
464 /**
465 * struct axiethernet_option - Used to set axi ethernet hardware options
466 * @opt: Option to be set.
467 * @reg: Register offset to be written for setting the option
468 * @m_or: Mask to be ORed for setting the option in the register
469 */
470 struct axienet_option {
471 u32 opt;
472 u32 reg;
473 u32 m_or;
474 };
475
476 /**
477 * axienet_ior - Memory mapped Axi Ethernet register read
478 * @lp: Pointer to axienet local structure
479 * @offset: Address offset from the base address of Axi Ethernet core
480 *
481 * Return: The contents of the Axi Ethernet register
482 *
483 * This function returns the contents of the corresponding register.
484 */
axienet_ior(struct axienet_local * lp,off_t offset)485 static inline u32 axienet_ior(struct axienet_local *lp, off_t offset)
486 {
487 return in_be32(lp->regs + offset);
488 }
489
490 /**
491 * axienet_iow - Memory mapped Axi Ethernet register write
492 * @lp: Pointer to axienet local structure
493 * @offset: Address offset from the base address of Axi Ethernet core
494 * @value: Value to be written into the Axi Ethernet register
495 *
496 * This function writes the desired value into the corresponding Axi Ethernet
497 * register.
498 */
axienet_iow(struct axienet_local * lp,off_t offset,u32 value)499 static inline void axienet_iow(struct axienet_local *lp, off_t offset,
500 u32 value)
501 {
502 out_be32((lp->regs + offset), value);
503 }
504
505 /* Function prototypes visible in xilinx_axienet_mdio.c for other files */
506 int axienet_mdio_setup(struct axienet_local *lp, struct device_node *np);
507 int axienet_mdio_wait_until_ready(struct axienet_local *lp);
508 void axienet_mdio_teardown(struct axienet_local *lp);
509
510 #endif /* XILINX_AXI_ENET_H */
511