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Searched refs:_offset (Results 1 – 25 of 48) sorted by relevance

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/drivers/clk/bcm/
Dclk-kona.h99 #define POLICY(_offset, _bit) \ argument
101 .offset = (_offset), \
159 #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
161 .offset = (_offset), \
171 #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
173 .offset = (_offset), \
182 #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
184 .offset = (_offset), \
193 #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ argument
195 .offset = (_offset), \
[all …]
/drivers/clk/tegra/
Dclk-tegra-periph.c130 #define MUX(_name, _parents, _offset, \ argument
132 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
137 #define MUX_FLAGS(_name, _parents, _offset,\ argument
139 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
144 #define MUX8(_name, _parents, _offset, \ argument
146 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
151 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
152 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
157 #define INT(_name, _parents, _offset, \ argument
159 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
[all …]
Dclk-tegra-audio.c62 #define AUDIO(_name, _offset) \ argument
66 .offset = _offset,\
81 #define AUDIO2X(_name, _num, _offset) \ argument
89 .div_offset = _offset,\
Dclk.h511 #define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ argument
526 .offset = _offset, \
532 #define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\ argument
536 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
Dclk-tegra30.c181 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ argument
183 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
187 #define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \ argument
189 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
193 #define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \ argument
195 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
200 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ argument
203 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
Dclk-tegra20.c144 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ argument
146 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
151 #define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \ argument
153 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
158 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ argument
161 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
/drivers/net/ethernet/mellanox/mlxsw/
Ditem.h250 #define MLXSW_ITEM16(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
252 .offset = _offset, \
266 #define MLXSW_ITEM16_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
269 .offset = _offset, \
291 #define MLXSW_ITEM32(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
293 .offset = _offset, \
307 #define MLXSW_ITEM32_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
310 .offset = _offset, \
332 #define MLXSW_ITEM64(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
334 .offset = _offset, \
[all …]
/drivers/staging/fsl-mc/include/
Dmc-cmd.h106 #define MC_EXT_OP(_ext, _param, _offset, _width, _type, _arg) \ argument
107 ((_ext)[_param] |= mc_enc((_offset), (_width), _arg))
109 #define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ argument
110 ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg))
112 #define MC_RSP_OP(_cmd, _param, _offset, _width, _type, _arg) \ argument
113 (_arg = (_type)mc_dec(_cmd.params[_param], (_offset), (_width)))
/drivers/pinctrl/mediatek/
Dpinctrl-mtk-common.h115 #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ argument
118 .offset = _offset, \
140 #define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) \ argument
143 .offset = _offset, \
163 #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ argument
168 .offset = _offset, \
/drivers/bcma/
Dsprom.c185 #define SPEX(_field, _offset, _mask, _shift) \ argument
186 bus->sprom._field = ((sprom[SPOFF(_offset)] & (_mask)) >> (_shift))
188 #define SPEX32(_field, _offset, _mask, _shift) \ argument
189 bus->sprom._field = ((((u32)sprom[SPOFF((_offset)+2)] << 16 | \
190 sprom[SPOFF(_offset)]) & (_mask)) >> (_shift))
192 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
194 SPEX(_field[0], _offset + 0, _mask, _shift); \
195 SPEX(_field[1], _offset + 2, _mask, _shift); \
196 SPEX(_field[2], _offset + 4, _mask, _shift); \
197 SPEX(_field[3], _offset + 6, _mask, _shift); \
[all …]
/drivers/video/fbdev/vermilion/
Dvermilion.h254 #define VML_READ32(_par, _offset) \ argument
255 (ioread32((_par)->vdc_mem + (_offset)))
256 #define VML_WRITE32(_par, _offset, _value) \ argument
257 iowrite32(_value, (_par)->vdc_mem + (_offset))
/drivers/usb/musb/
Dmusbhsdma.h42 #define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \ argument
43 (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
72 #define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \ argument
73 (MUSB_HSDMA_BASE + (_bchannel * 0x20) + _offset)
Dmusb_regs.h493 #define MUSB_INDEXED_OFFSET(_epnum, _offset) \ argument
494 (0x40 + (_offset))
497 #define MUSB_FLAT_OFFSET(_epnum, _offset) \ argument
498 (USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
/drivers/ssb/
Dpci.c172 #define SPEX16(_outvar, _offset, _mask, _shift) \ argument
173 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
174 #define SPEX32(_outvar, _offset, _mask, _shift) \ argument
175 out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
176 in[SPOFF(_offset)]) & (_mask)) >> (_shift))
177 #define SPEX(_outvar, _offset, _mask, _shift) \ argument
178 SPEX16(_outvar, _offset, _mask, _shift)
180 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
182 SPEX(_field[0], _offset + 0, _mask, _shift); \
183 SPEX(_field[1], _offset + 2, _mask, _shift); \
[all …]
/drivers/pinctrl/berlin/
Dberlin.h40 #define BERLIN_PINCTRL_GROUP(_name, _offset, _width, _lsb, ...) \ argument
43 .offset = _offset, \
/drivers/clk/st/
Dclkgen.h37 #define CLKGEN_FIELD(_offset, _mask, _shift) { \ argument
38 .offset = _offset, \
/drivers/net/wireless/realtek/rtlwifi/
Defuse.h96 void read_efuse_byte(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
101 void read_efuse(struct ieee80211_hw *hw, u16 _offset,
Defuse.c195 void read_efuse_byte(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf) in read_efuse_byte() argument
203 (_offset & 0xff)); in read_efuse_byte()
206 ((_offset >> 8) & 0x03) | (readbyte & 0xfc)); in read_efuse_byte()
227 void read_efuse(struct ieee80211_hw *hw, u16 _offset, u16 _size_byte, u8 *pbuf) in read_efuse() argument
246 if ((_offset + _size_byte) > rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]) { in read_efuse()
249 _offset, _size_byte); in read_efuse()
361 pbuf[i] = efuse_tbl[_offset + i]; in read_efuse()
/drivers/staging/rtl8723au/hal/
Drtl8723a_hal_init.c384 u16 _offset, u16 _size_byte, u8 *pbuf) in hal_ReadEFuse_WiFi() argument
395 if ((_offset + _size_byte) > EFUSE_MAP_LEN_8723A) { in hal_ReadEFuse_WiFi()
397 __func__, _offset, _size_byte); in hal_ReadEFuse_WiFi()
462 pbuf[i] = efuseTbl[_offset + i]; in hal_ReadEFuse_WiFi()
475 u16 _offset, u16 _size_byte, u8 *pbuf) in hal_ReadEFuse_BT() argument
487 if ((_offset + _size_byte) > EFUSE_BT_MAP_LEN) { in hal_ReadEFuse_BT()
489 __func__, _offset, _size_byte); in hal_ReadEFuse_BT()
576 pbuf[i] = efuseTbl[_offset + i]; in hal_ReadEFuse_BT()
592 u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf) in rtl8723a_readefuse() argument
595 hal_ReadEFuse_WiFi(padapter, _offset, _size_byte, pbuf); in rtl8723a_readefuse()
[all …]
/drivers/gpu/drm/msm/adreno/
Dadreno_gpu.h30 #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1 argument
/drivers/staging/rtl8723au/core/
Drtw_efuse.c114 void ReadEFuseByte23a(struct rtw_adapter *Adapter, u16 _offset, u8 *pbuf) in ReadEFuseByte23a() argument
121 rtl8723au_write8(Adapter, EFUSE_CTRL+1, (_offset & 0xff)); in ReadEFuseByte23a()
124 ((_offset >> 8) & 0x03) | (readbyte & 0xfc)); in ReadEFuseByte23a()
/drivers/net/ethernet/qlogic/qed/
Dqed_mcp.c27 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ argument
28 qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
31 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ argument
32 qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
/drivers/net/ethernet/brocade/bna/
Dbna_hw_defs.h293 #define BNA_TXQ_WI_L4_HDR_N_OFFSET(_hdr_size, _offset) \ argument
294 (((_hdr_size) << 10) | ((_offset) & 0x3FF))
/drivers/staging/rtl8188eu/include/
Drtw_efuse.h108 void efuse_ReadEFuse(struct adapter *Adapter, u8 efuseType, u16 _offset,
/drivers/staging/rtl8188eu/core/
Drtw_efuse.c95 efuse_phymap_to_logical(u8 *phymap, u16 _offset, u16 _size_byte, u8 *pbuf) in efuse_phymap_to_logical() argument
206 pbuf[i] = efuseTbl[_offset+i]; in efuse_phymap_to_logical()
316 void efuse_ReadEFuse(struct adapter *Adapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf) in efuse_ReadEFuse() argument
322 iol_read_efuse(Adapter, 0, _offset, _size_byte, pbuf); in efuse_ReadEFuse()

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