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Searched refs:amdgpu_ring_write (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Duvd_v5_0.c170 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
171 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
174 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
175 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
178 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
179 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
182 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v5_0_hw_init()
183 amdgpu_ring_write(ring, 0x8); in uvd_v5_0_hw_init()
185 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v5_0_hw_init()
186 amdgpu_ring_write(ring, 3); in uvd_v5_0_hw_init()
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Duvd_v6_0.c167 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
168 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
171 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
172 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
175 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
176 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
179 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v6_0_hw_init()
180 amdgpu_ring_write(ring, 0x8); in uvd_v6_0_hw_init()
182 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v6_0_hw_init()
183 amdgpu_ring_write(ring, 3); in uvd_v6_0_hw_init()
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Duvd_v4_2.c174 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
175 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
178 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
179 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
182 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
183 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
186 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v4_2_hw_init()
187 amdgpu_ring_write(ring, 0x8); in uvd_v4_2_hw_init()
189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v4_2_hw_init()
190 amdgpu_ring_write(ring, 3); in uvd_v4_2_hw_init()
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Dsdma_v2_4.c230 amdgpu_ring_write(ring, ring->nop | in sdma_v2_4_ring_insert_nop()
233 amdgpu_ring_write(ring, ring->nop); in sdma_v2_4_ring_insert_nop()
255 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | in sdma_v2_4_ring_emit_ib()
257 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc); in sdma_v2_4_ring_emit_ib()
258 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); in sdma_v2_4_ring_emit_ib()
259 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); in sdma_v2_4_ring_emit_ib()
260 amdgpu_ring_write(ring, next_rptr); in sdma_v2_4_ring_emit_ib()
265 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v2_4_ring_emit_ib()
268 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
269 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v2_4_ring_emit_ib()
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Dcik_sdma.c199 amdgpu_ring_write(ring, ring->nop | in cik_sdma_ring_insert_nop()
202 amdgpu_ring_write(ring, ring->nop); in cik_sdma_ring_insert_nop()
223 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); in cik_sdma_ring_emit_ib()
224 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in cik_sdma_ring_emit_ib()
225 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); in cik_sdma_ring_emit_ib()
226 amdgpu_ring_write(ring, 1); /* number of DWs to follow */ in cik_sdma_ring_emit_ib()
227 amdgpu_ring_write(ring, next_rptr); in cik_sdma_ring_emit_ib()
232 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); in cik_sdma_ring_emit_ib()
233 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ in cik_sdma_ring_emit_ib()
234 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); in cik_sdma_ring_emit_ib()
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Dsdma_v3_0.c341 amdgpu_ring_write(ring, ring->nop | in sdma_v3_0_ring_insert_nop()
344 amdgpu_ring_write(ring, ring->nop); in sdma_v3_0_ring_insert_nop()
365 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | in sdma_v3_0_ring_emit_ib()
367 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc); in sdma_v3_0_ring_emit_ib()
368 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); in sdma_v3_0_ring_emit_ib()
369 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); in sdma_v3_0_ring_emit_ib()
370 amdgpu_ring_write(ring, next_rptr); in sdma_v3_0_ring_emit_ib()
375 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v3_0_ring_emit_ib()
378 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v3_0_ring_emit_ib()
379 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v3_0_ring_emit_ib()
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Dgfx_v7_0.c2362 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v7_0_ring_test_ring()
2363 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); in gfx_v7_0_ring_test_ring()
2364 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v7_0_ring_test_ring()
2412 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_hdp_flush()
2413 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ in gfx_v7_0_ring_emit_hdp_flush()
2416 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); in gfx_v7_0_ring_emit_hdp_flush()
2417 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); in gfx_v7_0_ring_emit_hdp_flush()
2418 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2419 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2420 amdgpu_ring_write(ring, 0x20); /* poll interval */ in gfx_v7_0_ring_emit_hdp_flush()
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Dgfx_v8_0.c641 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v8_0_ring_test_ring()
642 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); in gfx_v8_0_ring_test_ring()
643 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v8_0_ring_test_ring()
3234 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_cp_gfx_start()
3235 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v8_0_cp_gfx_start()
3237 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v8_0_cp_gfx_start()
3238 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
3239 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
3244 amdgpu_ring_write(ring, in gfx_v8_0_cp_gfx_start()
3247 amdgpu_ring_write(ring, in gfx_v8_0_cp_gfx_start()
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Damdgpu_vce.c769 amdgpu_ring_write(ring, VCE_CMD_SEMAPHORE); in amdgpu_vce_ring_emit_semaphore()
770 amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF); in amdgpu_vce_ring_emit_semaphore()
771 amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF); in amdgpu_vce_ring_emit_semaphore()
772 amdgpu_ring_write(ring, 0x01003000 | (emit_wait ? 1 : 0)); in amdgpu_vce_ring_emit_semaphore()
774 amdgpu_ring_write(ring, VCE_CMD_END); in amdgpu_vce_ring_emit_semaphore()
788 amdgpu_ring_write(ring, VCE_CMD_IB); in amdgpu_vce_ring_emit_ib()
789 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in amdgpu_vce_ring_emit_ib()
790 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in amdgpu_vce_ring_emit_ib()
791 amdgpu_ring_write(ring, ib->length_dw); in amdgpu_vce_ring_emit_ib()
806 amdgpu_ring_write(ring, VCE_CMD_FENCE); in amdgpu_vce_ring_emit_fence()
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Damdgpu_ring.c144 amdgpu_ring_write(ring, ring->nop); in amdgpu_ring_insert_nop()
284 amdgpu_ring_write(ring, data[i]); in amdgpu_ring_restore()
Damdgpu.h2202 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) in amdgpu_ring_write() function