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Searched refs:anatop_base (Results 1 – 2 of 2) sorted by relevance

/drivers/clk/imx/
Dclk-vf610.c58 #define PFD_PLL1_BASE (anatop_base + 0x2b0)
59 #define PFD_PLL2_BASE (anatop_base + 0x100)
60 #define PFD_PLL3_BASE (anatop_base + 0xf0)
61 #define PLL1_CTRL (anatop_base + 0x270)
62 #define PLL2_CTRL (anatop_base + 0x30)
63 #define PLL3_CTRL (anatop_base + 0x10)
64 #define PLL4_CTRL (anatop_base + 0x70)
65 #define PLL5_CTRL (anatop_base + 0xe0)
66 #define PLL6_CTRL (anatop_base + 0xa0)
67 #define PLL7_CTRL (anatop_base + 0x20)
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Dclk-imx6sl.c107 static void __iomem *anatop_base; variable
140 if ((readl_relaxed(anatop_base + PLL_ARM) & in imx6sl_get_arm_divider_for_wait()
154 saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM); in imx6sl_enable_pll_arm()
157 writel_relaxed(val, anatop_base + PLL_ARM); in imx6sl_enable_pll_arm()
158 while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK)) in imx6sl_enable_pll_arm()
161 writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM); in imx6sl_enable_pll_arm()
212 anatop_base = base; in imx6sl_clocks_init()