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Searched refs:bankw (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/radeon/
Devergreen_cs.c176 unsigned bankw; member
268 palign = (8 * surf->bankw * track->npipes) * surf->mtilea; in evergreen_surface_check_2d()
347 switch (surf->bankw) { in evergreen_surface_value_conv_check()
348 case 0: surf->bankw = 1; break; in evergreen_surface_value_conv_check()
349 case 1: surf->bankw = 2; break; in evergreen_surface_value_conv_check()
350 case 2: surf->bankw = 4; break; in evergreen_surface_value_conv_check()
351 case 3: surf->bankw = 8; break; in evergreen_surface_value_conv_check()
354 __func__, __LINE__, prefix, surf->bankw); in evergreen_surface_value_conv_check()
410 surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
486 surf.bankw, surf.bankh, in evergreen_cs_track_validate_cb()
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Dradeon_object.c674 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; in radeon_bo_set_tiling_flags() local
676 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_set_tiling_flags()
681 switch (bankw) { in radeon_bo_set_tiling_flags()
Devergreen.c1106 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, in evergreen_tiling_fields() argument
1110 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in evergreen_tiling_fields()
1114 switch (*bankw) { in evergreen_tiling_fields()
1116 case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break; in evergreen_tiling_fields()
1117 case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break; in evergreen_tiling_fields()
1118 case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break; in evergreen_tiling_fields()
1119 case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break; in evergreen_tiling_fields()
Datombios_crtc.c1150 unsigned bankw, bankh, mtaspect, tile_split; in dce4_crtc_do_set_base() local
1264 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base()
1329 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); in dce4_crtc_do_set_base()
Dradeon.h347 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
/drivers/gpu/drm/amd/amdgpu/
Ddce_v8_0.c2122 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v8_0_crtc_do_set_base() local
2124 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v8_0_crtc_do_set_base()
2133 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT); in dce_v8_0_crtc_do_set_base()
Ddce_v10_0.c2165 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v10_0_crtc_do_set_base() local
2167 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base()
2178 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); in dce_v10_0_crtc_do_set_base()
Ddce_v11_0.c2153 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v11_0_crtc_do_set_base() local
2155 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base()
2166 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); in dce_v11_0_crtc_do_set_base()