1 /*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 * SOFTWARE.
30 */
31 #ifndef __IW_CXGB4_H__
32 #define __IW_CXGB4_H__
33
34 #include <linux/mutex.h>
35 #include <linux/list.h>
36 #include <linux/spinlock.h>
37 #include <linux/idr.h>
38 #include <linux/completion.h>
39 #include <linux/netdevice.h>
40 #include <linux/sched.h>
41 #include <linux/pci.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/inet.h>
44 #include <linux/wait.h>
45 #include <linux/kref.h>
46 #include <linux/timer.h>
47 #include <linux/io.h>
48
49 #include <asm/byteorder.h>
50
51 #include <net/net_namespace.h>
52
53 #include <rdma/ib_verbs.h>
54 #include <rdma/iw_cm.h>
55 #include <rdma/rdma_netlink.h>
56 #include <rdma/iw_portmap.h>
57
58 #include "cxgb4.h"
59 #include "cxgb4_uld.h"
60 #include "l2t.h"
61 #include "user.h"
62
63 #define DRV_NAME "iw_cxgb4"
64 #define MOD DRV_NAME ":"
65
66 extern int c4iw_debug;
67 #define PDBG(fmt, args...) \
68 do { \
69 if (c4iw_debug) \
70 printk(MOD fmt, ## args); \
71 } while (0)
72
73 #include "t4.h"
74
75 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
76 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
77
cplhdr(struct sk_buff * skb)78 static inline void *cplhdr(struct sk_buff *skb)
79 {
80 return skb->data;
81 }
82
83 #define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */
84 #define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */
85
86 struct c4iw_id_table {
87 u32 flags;
88 u32 start; /* logical minimal id */
89 u32 last; /* hint for find */
90 u32 max;
91 spinlock_t lock;
92 unsigned long *table;
93 };
94
95 struct c4iw_resource {
96 struct c4iw_id_table tpt_table;
97 struct c4iw_id_table qid_table;
98 struct c4iw_id_table pdid_table;
99 };
100
101 struct c4iw_qid_list {
102 struct list_head entry;
103 u32 qid;
104 };
105
106 struct c4iw_dev_ucontext {
107 struct list_head qpids;
108 struct list_head cqids;
109 struct mutex lock;
110 };
111
112 enum c4iw_rdev_flags {
113 T4_FATAL_ERROR = (1<<0),
114 T4_STATUS_PAGE_DISABLED = (1<<1),
115 };
116
117 struct c4iw_stat {
118 u64 total;
119 u64 cur;
120 u64 max;
121 u64 fail;
122 };
123
124 struct c4iw_stats {
125 struct mutex lock;
126 struct c4iw_stat qid;
127 struct c4iw_stat pd;
128 struct c4iw_stat stag;
129 struct c4iw_stat pbl;
130 struct c4iw_stat rqt;
131 struct c4iw_stat ocqp;
132 u64 db_full;
133 u64 db_empty;
134 u64 db_drop;
135 u64 db_state_transitions;
136 u64 db_fc_interruptions;
137 u64 tcam_full;
138 u64 act_ofld_conn_fails;
139 u64 pas_ofld_conn_fails;
140 u64 neg_adv;
141 };
142
143 struct c4iw_hw_queue {
144 int t4_eq_status_entries;
145 int t4_max_eq_size;
146 int t4_max_iq_size;
147 int t4_max_rq_size;
148 int t4_max_sq_size;
149 int t4_max_qp_depth;
150 int t4_max_cq_depth;
151 int t4_stat_len;
152 };
153
154 struct wr_log_entry {
155 struct timespec post_host_ts;
156 struct timespec poll_host_ts;
157 u64 post_sge_ts;
158 u64 cqe_sge_ts;
159 u64 poll_sge_ts;
160 u16 qid;
161 u16 wr_id;
162 u8 opcode;
163 u8 valid;
164 };
165
166 struct c4iw_rdev {
167 struct c4iw_resource resource;
168 u32 qpmask;
169 u32 cqmask;
170 struct c4iw_dev_ucontext uctx;
171 struct gen_pool *pbl_pool;
172 struct gen_pool *rqt_pool;
173 struct gen_pool *ocqp_pool;
174 u32 flags;
175 struct cxgb4_lld_info lldi;
176 unsigned long bar2_pa;
177 void __iomem *bar2_kva;
178 unsigned long oc_mw_pa;
179 void __iomem *oc_mw_kva;
180 struct c4iw_stats stats;
181 struct c4iw_hw_queue hw_queue;
182 struct t4_dev_status_page *status_page;
183 atomic_t wr_log_idx;
184 struct wr_log_entry *wr_log;
185 int wr_log_size;
186 };
187
c4iw_fatal_error(struct c4iw_rdev * rdev)188 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
189 {
190 return rdev->flags & T4_FATAL_ERROR;
191 }
192
c4iw_num_stags(struct c4iw_rdev * rdev)193 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
194 {
195 return (int)(rdev->lldi.vr->stag.size >> 5);
196 }
197
198 #define C4IW_WR_TO (60*HZ)
199
200 struct c4iw_wr_wait {
201 struct completion completion;
202 int ret;
203 };
204
c4iw_init_wr_wait(struct c4iw_wr_wait * wr_waitp)205 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
206 {
207 wr_waitp->ret = 0;
208 init_completion(&wr_waitp->completion);
209 }
210
c4iw_wake_up(struct c4iw_wr_wait * wr_waitp,int ret)211 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
212 {
213 wr_waitp->ret = ret;
214 complete(&wr_waitp->completion);
215 }
216
c4iw_wait_for_reply(struct c4iw_rdev * rdev,struct c4iw_wr_wait * wr_waitp,u32 hwtid,u32 qpid,const char * func)217 static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
218 struct c4iw_wr_wait *wr_waitp,
219 u32 hwtid, u32 qpid,
220 const char *func)
221 {
222 int ret;
223
224 if (c4iw_fatal_error(rdev)) {
225 wr_waitp->ret = -EIO;
226 goto out;
227 }
228
229 ret = wait_for_completion_timeout(&wr_waitp->completion, C4IW_WR_TO);
230 if (!ret) {
231 PDBG("%s - Device %s not responding (disabling device) - tid %u qpid %u\n",
232 func, pci_name(rdev->lldi.pdev), hwtid, qpid);
233 rdev->flags |= T4_FATAL_ERROR;
234 wr_waitp->ret = -EIO;
235 }
236 out:
237 if (wr_waitp->ret)
238 PDBG("%s: FW reply %d tid %u qpid %u\n",
239 pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid);
240 return wr_waitp->ret;
241 }
242
243 enum db_state {
244 NORMAL = 0,
245 FLOW_CONTROL = 1,
246 RECOVERY = 2,
247 STOPPED = 3
248 };
249
250 struct c4iw_dev {
251 struct ib_device ibdev;
252 struct c4iw_rdev rdev;
253 u32 device_cap_flags;
254 struct idr cqidr;
255 struct idr qpidr;
256 struct idr mmidr;
257 spinlock_t lock;
258 struct mutex db_mutex;
259 struct dentry *debugfs_root;
260 enum db_state db_state;
261 struct idr hwtid_idr;
262 struct idr atid_idr;
263 struct idr stid_idr;
264 struct list_head db_fc_list;
265 u32 avail_ird;
266 };
267
to_c4iw_dev(struct ib_device * ibdev)268 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
269 {
270 return container_of(ibdev, struct c4iw_dev, ibdev);
271 }
272
rdev_to_c4iw_dev(struct c4iw_rdev * rdev)273 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
274 {
275 return container_of(rdev, struct c4iw_dev, rdev);
276 }
277
get_chp(struct c4iw_dev * rhp,u32 cqid)278 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
279 {
280 return idr_find(&rhp->cqidr, cqid);
281 }
282
get_qhp(struct c4iw_dev * rhp,u32 qpid)283 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
284 {
285 return idr_find(&rhp->qpidr, qpid);
286 }
287
get_mhp(struct c4iw_dev * rhp,u32 mmid)288 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
289 {
290 return idr_find(&rhp->mmidr, mmid);
291 }
292
_insert_handle(struct c4iw_dev * rhp,struct idr * idr,void * handle,u32 id,int lock)293 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
294 void *handle, u32 id, int lock)
295 {
296 int ret;
297
298 if (lock) {
299 idr_preload(GFP_KERNEL);
300 spin_lock_irq(&rhp->lock);
301 }
302
303 ret = idr_alloc(idr, handle, id, id + 1, GFP_ATOMIC);
304
305 if (lock) {
306 spin_unlock_irq(&rhp->lock);
307 idr_preload_end();
308 }
309
310 BUG_ON(ret == -ENOSPC);
311 return ret < 0 ? ret : 0;
312 }
313
insert_handle(struct c4iw_dev * rhp,struct idr * idr,void * handle,u32 id)314 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
315 void *handle, u32 id)
316 {
317 return _insert_handle(rhp, idr, handle, id, 1);
318 }
319
insert_handle_nolock(struct c4iw_dev * rhp,struct idr * idr,void * handle,u32 id)320 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
321 void *handle, u32 id)
322 {
323 return _insert_handle(rhp, idr, handle, id, 0);
324 }
325
_remove_handle(struct c4iw_dev * rhp,struct idr * idr,u32 id,int lock)326 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
327 u32 id, int lock)
328 {
329 if (lock)
330 spin_lock_irq(&rhp->lock);
331 idr_remove(idr, id);
332 if (lock)
333 spin_unlock_irq(&rhp->lock);
334 }
335
remove_handle(struct c4iw_dev * rhp,struct idr * idr,u32 id)336 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
337 {
338 _remove_handle(rhp, idr, id, 1);
339 }
340
remove_handle_nolock(struct c4iw_dev * rhp,struct idr * idr,u32 id)341 static inline void remove_handle_nolock(struct c4iw_dev *rhp,
342 struct idr *idr, u32 id)
343 {
344 _remove_handle(rhp, idr, id, 0);
345 }
346
347 extern uint c4iw_max_read_depth;
348
cur_max_read_depth(struct c4iw_dev * dev)349 static inline int cur_max_read_depth(struct c4iw_dev *dev)
350 {
351 return min(dev->rdev.lldi.max_ordird_qp, c4iw_max_read_depth);
352 }
353
354 struct c4iw_pd {
355 struct ib_pd ibpd;
356 u32 pdid;
357 struct c4iw_dev *rhp;
358 };
359
to_c4iw_pd(struct ib_pd * ibpd)360 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
361 {
362 return container_of(ibpd, struct c4iw_pd, ibpd);
363 }
364
365 struct tpt_attributes {
366 u64 len;
367 u64 va_fbo;
368 enum fw_ri_mem_perms perms;
369 u32 stag;
370 u32 pdid;
371 u32 qpid;
372 u32 pbl_addr;
373 u32 pbl_size;
374 u32 state:1;
375 u32 type:2;
376 u32 rsvd:1;
377 u32 remote_invaliate_disable:1;
378 u32 zbva:1;
379 u32 mw_bind_enable:1;
380 u32 page_size:5;
381 };
382
383 struct c4iw_mr {
384 struct ib_mr ibmr;
385 struct ib_umem *umem;
386 struct c4iw_dev *rhp;
387 u64 kva;
388 struct tpt_attributes attr;
389 u64 *mpl;
390 dma_addr_t mpl_addr;
391 u32 max_mpl_len;
392 u32 mpl_len;
393 };
394
to_c4iw_mr(struct ib_mr * ibmr)395 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
396 {
397 return container_of(ibmr, struct c4iw_mr, ibmr);
398 }
399
400 struct c4iw_mw {
401 struct ib_mw ibmw;
402 struct c4iw_dev *rhp;
403 u64 kva;
404 struct tpt_attributes attr;
405 };
406
to_c4iw_mw(struct ib_mw * ibmw)407 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
408 {
409 return container_of(ibmw, struct c4iw_mw, ibmw);
410 }
411
412 struct c4iw_cq {
413 struct ib_cq ibcq;
414 struct c4iw_dev *rhp;
415 struct t4_cq cq;
416 spinlock_t lock;
417 spinlock_t comp_handler_lock;
418 atomic_t refcnt;
419 wait_queue_head_t wait;
420 };
421
to_c4iw_cq(struct ib_cq * ibcq)422 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
423 {
424 return container_of(ibcq, struct c4iw_cq, ibcq);
425 }
426
427 struct c4iw_mpa_attributes {
428 u8 initiator;
429 u8 recv_marker_enabled;
430 u8 xmit_marker_enabled;
431 u8 crc_enabled;
432 u8 enhanced_rdma_conn;
433 u8 version;
434 u8 p2p_type;
435 };
436
437 struct c4iw_qp_attributes {
438 u32 scq;
439 u32 rcq;
440 u32 sq_num_entries;
441 u32 rq_num_entries;
442 u32 sq_max_sges;
443 u32 sq_max_sges_rdma_write;
444 u32 rq_max_sges;
445 u32 state;
446 u8 enable_rdma_read;
447 u8 enable_rdma_write;
448 u8 enable_bind;
449 u8 enable_mmid0_fastreg;
450 u32 max_ord;
451 u32 max_ird;
452 u32 pd;
453 u32 next_state;
454 char terminate_buffer[52];
455 u32 terminate_msg_len;
456 u8 is_terminate_local;
457 struct c4iw_mpa_attributes mpa_attr;
458 struct c4iw_ep *llp_stream_handle;
459 u8 layer_etype;
460 u8 ecode;
461 u16 sq_db_inc;
462 u16 rq_db_inc;
463 u8 send_term;
464 };
465
466 struct c4iw_qp {
467 struct ib_qp ibqp;
468 struct list_head db_fc_entry;
469 struct c4iw_dev *rhp;
470 struct c4iw_ep *ep;
471 struct c4iw_qp_attributes attr;
472 struct t4_wq wq;
473 spinlock_t lock;
474 struct mutex mutex;
475 atomic_t refcnt;
476 wait_queue_head_t wait;
477 struct timer_list timer;
478 int sq_sig_all;
479 };
480
to_c4iw_qp(struct ib_qp * ibqp)481 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
482 {
483 return container_of(ibqp, struct c4iw_qp, ibqp);
484 }
485
486 struct c4iw_ucontext {
487 struct ib_ucontext ibucontext;
488 struct c4iw_dev_ucontext uctx;
489 u32 key;
490 spinlock_t mmap_lock;
491 struct list_head mmaps;
492 };
493
to_c4iw_ucontext(struct ib_ucontext * c)494 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
495 {
496 return container_of(c, struct c4iw_ucontext, ibucontext);
497 }
498
499 struct c4iw_mm_entry {
500 struct list_head entry;
501 u64 addr;
502 u32 key;
503 unsigned len;
504 };
505
remove_mmap(struct c4iw_ucontext * ucontext,u32 key,unsigned len)506 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
507 u32 key, unsigned len)
508 {
509 struct list_head *pos, *nxt;
510 struct c4iw_mm_entry *mm;
511
512 spin_lock(&ucontext->mmap_lock);
513 list_for_each_safe(pos, nxt, &ucontext->mmaps) {
514
515 mm = list_entry(pos, struct c4iw_mm_entry, entry);
516 if (mm->key == key && mm->len == len) {
517 list_del_init(&mm->entry);
518 spin_unlock(&ucontext->mmap_lock);
519 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
520 key, (unsigned long long) mm->addr, mm->len);
521 return mm;
522 }
523 }
524 spin_unlock(&ucontext->mmap_lock);
525 return NULL;
526 }
527
insert_mmap(struct c4iw_ucontext * ucontext,struct c4iw_mm_entry * mm)528 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
529 struct c4iw_mm_entry *mm)
530 {
531 spin_lock(&ucontext->mmap_lock);
532 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
533 mm->key, (unsigned long long) mm->addr, mm->len);
534 list_add_tail(&mm->entry, &ucontext->mmaps);
535 spin_unlock(&ucontext->mmap_lock);
536 }
537
538 enum c4iw_qp_attr_mask {
539 C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
540 C4IW_QP_ATTR_SQ_DB = 1<<1,
541 C4IW_QP_ATTR_RQ_DB = 1<<2,
542 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
543 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
544 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
545 C4IW_QP_ATTR_MAX_ORD = 1 << 11,
546 C4IW_QP_ATTR_MAX_IRD = 1 << 12,
547 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
548 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
549 C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
550 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
551 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
552 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
553 C4IW_QP_ATTR_MAX_ORD |
554 C4IW_QP_ATTR_MAX_IRD |
555 C4IW_QP_ATTR_LLP_STREAM_HANDLE |
556 C4IW_QP_ATTR_STREAM_MSG_BUFFER |
557 C4IW_QP_ATTR_MPA_ATTR |
558 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
559 };
560
561 int c4iw_modify_qp(struct c4iw_dev *rhp,
562 struct c4iw_qp *qhp,
563 enum c4iw_qp_attr_mask mask,
564 struct c4iw_qp_attributes *attrs,
565 int internal);
566
567 enum c4iw_qp_state {
568 C4IW_QP_STATE_IDLE,
569 C4IW_QP_STATE_RTS,
570 C4IW_QP_STATE_ERROR,
571 C4IW_QP_STATE_TERMINATE,
572 C4IW_QP_STATE_CLOSING,
573 C4IW_QP_STATE_TOT
574 };
575
c4iw_convert_state(enum ib_qp_state ib_state)576 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
577 {
578 switch (ib_state) {
579 case IB_QPS_RESET:
580 case IB_QPS_INIT:
581 return C4IW_QP_STATE_IDLE;
582 case IB_QPS_RTS:
583 return C4IW_QP_STATE_RTS;
584 case IB_QPS_SQD:
585 return C4IW_QP_STATE_CLOSING;
586 case IB_QPS_SQE:
587 return C4IW_QP_STATE_TERMINATE;
588 case IB_QPS_ERR:
589 return C4IW_QP_STATE_ERROR;
590 default:
591 return -1;
592 }
593 }
594
to_ib_qp_state(int c4iw_qp_state)595 static inline int to_ib_qp_state(int c4iw_qp_state)
596 {
597 switch (c4iw_qp_state) {
598 case C4IW_QP_STATE_IDLE:
599 return IB_QPS_INIT;
600 case C4IW_QP_STATE_RTS:
601 return IB_QPS_RTS;
602 case C4IW_QP_STATE_CLOSING:
603 return IB_QPS_SQD;
604 case C4IW_QP_STATE_TERMINATE:
605 return IB_QPS_SQE;
606 case C4IW_QP_STATE_ERROR:
607 return IB_QPS_ERR;
608 }
609 return IB_QPS_ERR;
610 }
611
c4iw_ib_to_tpt_access(int a)612 static inline u32 c4iw_ib_to_tpt_access(int a)
613 {
614 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
615 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
616 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
617 FW_RI_MEM_ACCESS_LOCAL_READ;
618 }
619
c4iw_ib_to_tpt_bind_access(int acc)620 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
621 {
622 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
623 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
624 }
625
626 enum c4iw_mmid_state {
627 C4IW_STAG_STATE_VALID,
628 C4IW_STAG_STATE_INVALID
629 };
630
631 #define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
632
633 #define MPA_KEY_REQ "MPA ID Req Frame"
634 #define MPA_KEY_REP "MPA ID Rep Frame"
635
636 #define MPA_MAX_PRIVATE_DATA 256
637 #define MPA_ENHANCED_RDMA_CONN 0x10
638 #define MPA_REJECT 0x20
639 #define MPA_CRC 0x40
640 #define MPA_MARKERS 0x80
641 #define MPA_FLAGS_MASK 0xE0
642
643 #define MPA_V2_PEER2PEER_MODEL 0x8000
644 #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000
645 #define MPA_V2_RDMA_WRITE_RTR 0x8000
646 #define MPA_V2_RDMA_READ_RTR 0x4000
647 #define MPA_V2_IRD_ORD_MASK 0x3FFF
648
649 #define c4iw_put_ep(ep) { \
650 PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__, \
651 ep, atomic_read(&((ep)->kref.refcount))); \
652 WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \
653 kref_put(&((ep)->kref), _c4iw_free_ep); \
654 }
655
656 #define c4iw_get_ep(ep) { \
657 PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
658 ep, atomic_read(&((ep)->kref.refcount))); \
659 kref_get(&((ep)->kref)); \
660 }
661 void _c4iw_free_ep(struct kref *kref);
662
663 struct mpa_message {
664 u8 key[16];
665 u8 flags;
666 u8 revision;
667 __be16 private_data_size;
668 u8 private_data[0];
669 };
670
671 struct mpa_v2_conn_params {
672 __be16 ird;
673 __be16 ord;
674 };
675
676 struct terminate_message {
677 u8 layer_etype;
678 u8 ecode;
679 __be16 hdrct_rsvd;
680 u8 len_hdrs[0];
681 };
682
683 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
684
685 enum c4iw_layers_types {
686 LAYER_RDMAP = 0x00,
687 LAYER_DDP = 0x10,
688 LAYER_MPA = 0x20,
689 RDMAP_LOCAL_CATA = 0x00,
690 RDMAP_REMOTE_PROT = 0x01,
691 RDMAP_REMOTE_OP = 0x02,
692 DDP_LOCAL_CATA = 0x00,
693 DDP_TAGGED_ERR = 0x01,
694 DDP_UNTAGGED_ERR = 0x02,
695 DDP_LLP = 0x03
696 };
697
698 enum c4iw_rdma_ecodes {
699 RDMAP_INV_STAG = 0x00,
700 RDMAP_BASE_BOUNDS = 0x01,
701 RDMAP_ACC_VIOL = 0x02,
702 RDMAP_STAG_NOT_ASSOC = 0x03,
703 RDMAP_TO_WRAP = 0x04,
704 RDMAP_INV_VERS = 0x05,
705 RDMAP_INV_OPCODE = 0x06,
706 RDMAP_STREAM_CATA = 0x07,
707 RDMAP_GLOBAL_CATA = 0x08,
708 RDMAP_CANT_INV_STAG = 0x09,
709 RDMAP_UNSPECIFIED = 0xff
710 };
711
712 enum c4iw_ddp_ecodes {
713 DDPT_INV_STAG = 0x00,
714 DDPT_BASE_BOUNDS = 0x01,
715 DDPT_STAG_NOT_ASSOC = 0x02,
716 DDPT_TO_WRAP = 0x03,
717 DDPT_INV_VERS = 0x04,
718 DDPU_INV_QN = 0x01,
719 DDPU_INV_MSN_NOBUF = 0x02,
720 DDPU_INV_MSN_RANGE = 0x03,
721 DDPU_INV_MO = 0x04,
722 DDPU_MSG_TOOBIG = 0x05,
723 DDPU_INV_VERS = 0x06
724 };
725
726 enum c4iw_mpa_ecodes {
727 MPA_CRC_ERR = 0x02,
728 MPA_MARKER_ERR = 0x03,
729 MPA_LOCAL_CATA = 0x05,
730 MPA_INSUFF_IRD = 0x06,
731 MPA_NOMATCH_RTR = 0x07,
732 };
733
734 enum c4iw_ep_state {
735 IDLE = 0,
736 LISTEN,
737 CONNECTING,
738 MPA_REQ_WAIT,
739 MPA_REQ_SENT,
740 MPA_REQ_RCVD,
741 MPA_REP_SENT,
742 FPDU_MODE,
743 ABORTING,
744 CLOSING,
745 MORIBUND,
746 DEAD,
747 };
748
749 enum c4iw_ep_flags {
750 PEER_ABORT_IN_PROGRESS = 0,
751 ABORT_REQ_IN_PROGRESS = 1,
752 RELEASE_RESOURCES = 2,
753 CLOSE_SENT = 3,
754 TIMEOUT = 4,
755 QP_REFERENCED = 5,
756 RELEASE_MAPINFO = 6,
757 };
758
759 enum c4iw_ep_history {
760 ACT_OPEN_REQ = 0,
761 ACT_OFLD_CONN = 1,
762 ACT_OPEN_RPL = 2,
763 ACT_ESTAB = 3,
764 PASS_ACCEPT_REQ = 4,
765 PASS_ESTAB = 5,
766 ABORT_UPCALL = 6,
767 ESTAB_UPCALL = 7,
768 CLOSE_UPCALL = 8,
769 ULP_ACCEPT = 9,
770 ULP_REJECT = 10,
771 TIMEDOUT = 11,
772 PEER_ABORT = 12,
773 PEER_CLOSE = 13,
774 CONNREQ_UPCALL = 14,
775 ABORT_CONN = 15,
776 DISCONN_UPCALL = 16,
777 EP_DISC_CLOSE = 17,
778 EP_DISC_ABORT = 18,
779 CONN_RPL_UPCALL = 19,
780 ACT_RETRY_NOMEM = 20,
781 ACT_RETRY_INUSE = 21
782 };
783
784 struct c4iw_ep_common {
785 struct iw_cm_id *cm_id;
786 struct c4iw_qp *qp;
787 struct c4iw_dev *dev;
788 enum c4iw_ep_state state;
789 struct kref kref;
790 struct mutex mutex;
791 struct sockaddr_storage local_addr;
792 struct sockaddr_storage remote_addr;
793 struct sockaddr_storage mapped_local_addr;
794 struct sockaddr_storage mapped_remote_addr;
795 struct c4iw_wr_wait wr_wait;
796 unsigned long flags;
797 unsigned long history;
798 };
799
800 struct c4iw_listen_ep {
801 struct c4iw_ep_common com;
802 unsigned int stid;
803 int backlog;
804 };
805
806 struct c4iw_ep_stats {
807 unsigned connect_neg_adv;
808 unsigned abort_neg_adv;
809 };
810
811 struct c4iw_ep {
812 struct c4iw_ep_common com;
813 struct c4iw_ep *parent_ep;
814 struct timer_list timer;
815 struct list_head entry;
816 unsigned int atid;
817 u32 hwtid;
818 u32 snd_seq;
819 u32 rcv_seq;
820 struct l2t_entry *l2t;
821 struct dst_entry *dst;
822 struct sk_buff *mpa_skb;
823 struct c4iw_mpa_attributes mpa_attr;
824 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
825 unsigned int mpa_pkt_len;
826 u32 ird;
827 u32 ord;
828 u32 smac_idx;
829 u32 tx_chan;
830 u32 mtu;
831 u16 mss;
832 u16 emss;
833 u16 plen;
834 u16 rss_qid;
835 u16 txq_idx;
836 u16 ctrlq_idx;
837 u8 tos;
838 u8 retry_with_mpa_v1;
839 u8 tried_with_mpa_v1;
840 unsigned int retry_count;
841 int snd_win;
842 int rcv_win;
843 struct c4iw_ep_stats stats;
844 };
845
print_addr(struct c4iw_ep_common * epc,const char * func,const char * msg)846 static inline void print_addr(struct c4iw_ep_common *epc, const char *func,
847 const char *msg)
848 {
849
850 #define SINA(a) (&(((struct sockaddr_in *)(a))->sin_addr.s_addr))
851 #define SINP(a) ntohs(((struct sockaddr_in *)(a))->sin_port)
852 #define SIN6A(a) (&(((struct sockaddr_in6 *)(a))->sin6_addr))
853 #define SIN6P(a) ntohs(((struct sockaddr_in6 *)(a))->sin6_port)
854
855 if (c4iw_debug) {
856 switch (epc->local_addr.ss_family) {
857 case AF_INET:
858 PDBG("%s %s %pI4:%u/%u <-> %pI4:%u/%u\n",
859 func, msg, SINA(&epc->local_addr),
860 SINP(&epc->local_addr),
861 SINP(&epc->mapped_local_addr),
862 SINA(&epc->remote_addr),
863 SINP(&epc->remote_addr),
864 SINP(&epc->mapped_remote_addr));
865 break;
866 case AF_INET6:
867 PDBG("%s %s %pI6:%u/%u <-> %pI6:%u/%u\n",
868 func, msg, SIN6A(&epc->local_addr),
869 SIN6P(&epc->local_addr),
870 SIN6P(&epc->mapped_local_addr),
871 SIN6A(&epc->remote_addr),
872 SIN6P(&epc->remote_addr),
873 SIN6P(&epc->mapped_remote_addr));
874 break;
875 default:
876 break;
877 }
878 }
879 #undef SINA
880 #undef SINP
881 #undef SIN6A
882 #undef SIN6P
883 }
884
to_ep(struct iw_cm_id * cm_id)885 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
886 {
887 return cm_id->provider_data;
888 }
889
to_listen_ep(struct iw_cm_id * cm_id)890 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
891 {
892 return cm_id->provider_data;
893 }
894
compute_wscale(int win)895 static inline int compute_wscale(int win)
896 {
897 int wscale = 0;
898
899 while (wscale < 14 && (65535<<wscale) < win)
900 wscale++;
901 return wscale;
902 }
903
ocqp_supported(const struct cxgb4_lld_info * infop)904 static inline int ocqp_supported(const struct cxgb4_lld_info *infop)
905 {
906 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
907 return infop->vr->ocq.size > 0;
908 #else
909 return 0;
910 #endif
911 }
912
913 u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
914 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
915 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
916 u32 reserved, u32 flags);
917 void c4iw_id_table_free(struct c4iw_id_table *alloc);
918
919 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);
920
921 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
922 struct l2t_entry *l2t);
923 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
924 struct c4iw_dev_ucontext *uctx);
925 u32 c4iw_get_resource(struct c4iw_id_table *id_table);
926 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
927 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
928 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
929 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
930 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
931 int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev);
932 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
933 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
934 void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev);
935 void c4iw_destroy_resource(struct c4iw_resource *rscp);
936 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
937 int c4iw_register_device(struct c4iw_dev *dev);
938 void c4iw_unregister_device(struct c4iw_dev *dev);
939 int __init c4iw_cm_init(void);
940 void c4iw_cm_term(void);
941 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
942 struct c4iw_dev_ucontext *uctx);
943 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
944 struct c4iw_dev_ucontext *uctx);
945 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
946 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
947 struct ib_send_wr **bad_wr);
948 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
949 struct ib_recv_wr **bad_wr);
950 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
951 struct ib_mw_bind *mw_bind);
952 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
953 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
954 int c4iw_destroy_listen(struct iw_cm_id *cm_id);
955 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
956 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
957 void c4iw_qp_add_ref(struct ib_qp *qp);
958 void c4iw_qp_rem_ref(struct ib_qp *qp);
959 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd,
960 enum ib_mr_type mr_type,
961 u32 max_num_sg);
962 int c4iw_map_mr_sg(struct ib_mr *ibmr,
963 struct scatterlist *sg,
964 int sg_nents);
965 int c4iw_dealloc_mw(struct ib_mw *mw);
966 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type);
967 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
968 u64 length, u64 virt, int acc,
969 struct ib_udata *udata);
970 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
971 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
972 struct ib_phys_buf *buffer_list,
973 int num_phys_buf,
974 int acc,
975 u64 *iova_start);
976 int c4iw_reregister_phys_mem(struct ib_mr *mr,
977 int mr_rereg_mask,
978 struct ib_pd *pd,
979 struct ib_phys_buf *buffer_list,
980 int num_phys_buf,
981 int acc, u64 *iova_start);
982 int c4iw_dereg_mr(struct ib_mr *ib_mr);
983 int c4iw_destroy_cq(struct ib_cq *ib_cq);
984 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev,
985 const struct ib_cq_init_attr *attr,
986 struct ib_ucontext *ib_context,
987 struct ib_udata *udata);
988 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
989 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
990 int c4iw_destroy_qp(struct ib_qp *ib_qp);
991 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
992 struct ib_qp_init_attr *attrs,
993 struct ib_udata *udata);
994 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
995 int attr_mask, struct ib_udata *udata);
996 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
997 int attr_mask, struct ib_qp_init_attr *init_attr);
998 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
999 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
1000 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
1001 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
1002 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
1003 u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size);
1004 void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size);
1005 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
1006 void c4iw_flush_hw_cq(struct c4iw_cq *chp);
1007 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
1008 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
1009 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
1010 int c4iw_flush_sq(struct c4iw_qp *qhp);
1011 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
1012 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
1013 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
1014 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
1015 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
1016 struct c4iw_dev_ucontext *uctx);
1017 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
1018 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
1019 struct c4iw_dev_ucontext *uctx);
1020 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
1021
1022 extern struct cxgb4_client t4c_client;
1023 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
1024 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
1025 enum cxgb4_bar2_qtype qtype,
1026 unsigned int *pbar2_qid, u64 *pbar2_pa);
1027 extern void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe);
1028 extern int c4iw_wr_log;
1029 extern int db_fc_threshold;
1030 extern int db_coalescing_threshold;
1031 extern int use_dsgl;
1032
1033
1034 #endif
1035