| /drivers/net/ethernet/mellanox/mlx4/ |
| D | main.c | 176 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { in mlx4_check_port_params()
177 for (i = 0; i < dev->caps.num_ports - 1; i++) { in mlx4_check_port_params()
185 for (i = 0; i < dev->caps.num_ports; i++) { in mlx4_check_port_params()
186 if (!(port_type[i] & dev->caps.supported_type[i+1])) { in mlx4_check_port_params()
199 for (i = 1; i <= dev->caps.num_ports; ++i) in mlx4_set_port_mask()
200 dev->caps.port_mask[i] = dev->caps.port_type[i]; in mlx4_set_port_mask()
212 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { in mlx4_query_func()
228 struct mlx4_caps *dev_cap = &dev->caps; in mlx4_enable_cqe_eqe_stride()
264 dev->caps.vl_cap[port] = port_cap->max_vl; in _mlx4_dev_port()
265 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu; in _mlx4_dev_port()
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| D | qp.c | 249 flags &= dev->caps.alloc_res_qp_mask; in mlx4_qp_reserve_range()
414 (dev->caps.num_qps - 1), qp); in mlx4_qp_alloc()
456 if (!(dev->caps.flags2 in mlx4_update_qp()
484 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP)) { in mlx4_update_qp()
512 radix_tree_delete(&dev->qp_table_tree, qp->qpn & (dev->caps.num_qps - 1)); in mlx4_qp_remove()
563 err = mlx4_bitmap_init(*bitmap + MLX4_QP_TABLE_ZONE_GENERAL, dev->caps.num_qps, in mlx4_create_zones()
583 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], in mlx4_create_zones()
600 last_offset = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; in mlx4_create_zones()
763 u32 max_table_offset = dev->caps.dmfs_high_rate_qpn_base + in mlx4_init_qp_table()
764 dev->caps.dmfs_high_rate_qpn_range; in mlx4_init_qp_table()
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| D | pd.c | 122 return mlx4_bitmap_init(&priv->pd_bitmap, dev->caps.num_pds, in mlx4_init_pd_table()
124 dev->caps.reserved_pds, 0); in mlx4_init_pd_table()
137 (1 << 16) - 1, dev->caps.reserved_xrcds + 1, 0); in mlx4_init_xrcd_table()
156 dev->caps.uar_page_size); in mlx4_uar_alloc()
221 bf->buf_size = dev->caps.bf_reg_size / 2; in mlx4_bf_alloc()
222 bf->reg = uar->bf_map + idx * dev->caps.bf_reg_size; in mlx4_bf_alloc()
223 if (uar->free_bf_bmap == (1 << dev->caps.bf_regs_per_page) - 1) in mlx4_bf_alloc()
253 idx = (bf->reg - bf->uar->bf_map) / dev->caps.bf_reg_size; in mlx4_bf_free()
272 if (dev->caps.num_uars <= 128) { in mlx4_init_uar_table()
274 dev->caps.num_uars); in mlx4_init_uar_table()
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| D | fw.c | 327 find_first_bit(actv_ports.ports, dev->caps.num_ports); in mlx4_QUERY_FUNC_CAP_wrapper()
355 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier], in mlx4_QUERY_FUNC_CAP_wrapper()
358 if (dev->caps.phv_bit[port]) { in mlx4_QUERY_FUNC_CAP_wrapper()
376 bitmap_weight(actv_ports.ports, dev->caps.num_ports), in mlx4_QUERY_FUNC_CAP_wrapper()
377 dev->caps.num_ports); in mlx4_QUERY_FUNC_CAP_wrapper()
380 size = dev->caps.function_caps; /* set PF behaviours */ in mlx4_QUERY_FUNC_CAP_wrapper()
388 size = dev->caps.num_qps; in mlx4_QUERY_FUNC_CAP_wrapper()
393 size = dev->caps.num_srqs; in mlx4_QUERY_FUNC_CAP_wrapper()
398 size = dev->caps.num_cqs; in mlx4_QUERY_FUNC_CAP_wrapper()
401 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) || in mlx4_QUERY_FUNC_CAP_wrapper()
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| D | profile.c | 183 dev->caps.num_qps = profile[i].num; in mlx4_make_profile()
192 dev->caps.max_qp_dest_rdma = 1 << priv->qp_table.rdmarc_shift; in mlx4_make_profile()
204 dev->caps.num_srqs = profile[i].num; in mlx4_make_profile()
209 dev->caps.num_cqs = profile[i].num; in mlx4_make_profile()
219 dev->caps.num_eqs = roundup_pow_of_two( in mlx4_make_profile()
224 init_hca->log_num_eqs = ilog2(dev->caps.num_eqs); in mlx4_make_profile()
228 dev->caps.num_mpts = profile[i].num; in mlx4_make_profile()
237 dev->caps.num_mtts = profile[i].num; in mlx4_make_profile()
246 if (dev->caps.steering_mode == in mlx4_make_profile()
248 dev->caps.num_mgms = profile[i].num; in mlx4_make_profile()
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| D | eq.c | 89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV) in get_async_ev_mask()
91 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) in get_async_ev_mask()
217 slave == dev->caps.function || in mlx4_slave_event()
305 if (slave >= dev->num_slaves || port > dev->caps.num_ports || in mlx4_get_slave_port_state()
322 if (slave >= dev->num_slaves || port > dev->caps.num_ports || in mlx4_set_slave_port_state()
368 if (slave >= dev->num_slaves || port > dev->caps.num_ports || in set_and_calc_slave_port_state()
498 int eqe_size = dev->caps.eqe_size; in mlx4_eq_int()
500 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor, eqe_size))) { in mlx4_eq_int()
535 if (!ret && slave != dev->caps.function) { in mlx4_eq_int()
570 if (!ret && slave != dev->caps.function) { in mlx4_eq_int()
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| D | sense.c | 72 for (i = 1; i <= dev->caps.num_ports; i++) { in mlx4_do_sense_ports()
75 dev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { in mlx4_do_sense_ports()
86 for (i = 0; i < dev->caps.num_ports; i++) in mlx4_do_sense_ports()
101 mlx4_do_sense_ports(dev, stype, &dev->caps.port_type[1]); in mlx4_sense_port()
120 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) in mlx4_start_sense()
139 for (port = 1; port <= dev->caps.num_ports; port++) in mlx4_sense_init()
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| D | port.c | 65 table->max = 1 << dev->caps.log_num_macs; in mlx4_init_mac_table()
78 table->max = (1 << dev->caps.log_num_vlans) - MLX4_VLAN_REGULAR; in mlx4_init_vlan_table()
248 return dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] + in mlx4_get_base_qpn()
249 (port - 1) * (1 << dev->caps.log_num_macs); in mlx4_get_base_qpn()
259 if (port < 1 || port > dev->caps.num_ports) { in __mlx4_unregister_mac()
498 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps) in mlx4_get_port_ib_caps() argument
527 *caps = *(__be32 *) (outbuf + 84); in mlx4_get_port_ib_caps()
549 max_port_p_one = find_first_bit(actv_ports.ports, dev->caps.num_ports) + in mlx4_get_slave_num_gids()
550 bitmap_weight(actv_ports.ports, dev->caps.num_ports) + 1; in mlx4_get_slave_num_gids()
555 bitmap_zero(exclusive_ports.ports, dev->caps.num_ports); in mlx4_get_slave_num_gids()
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| /drivers/net/wireless/ath/ath5k/ |
| D | caps.c | 35 struct ath5k_capabilities *caps = &ah->ah_capabilities; in ath5k_hw_set_capabilities() local
39 ee_header = caps->cap_eeprom.ee_header; in ath5k_hw_set_capabilities()
46 caps->cap_range.range_5ghz_min = 5120; in ath5k_hw_set_capabilities()
47 caps->cap_range.range_5ghz_max = 5430; in ath5k_hw_set_capabilities()
48 caps->cap_range.range_2ghz_min = 0; in ath5k_hw_set_capabilities()
49 caps->cap_range.range_2ghz_max = 0; in ath5k_hw_set_capabilities()
52 __set_bit(AR5K_MODE_11A, caps->cap_mode); in ath5k_hw_set_capabilities()
69 if (ath_is_49ghz_allowed(caps->cap_eeprom.ee_regdomain)) in ath5k_hw_set_capabilities()
70 caps->cap_range.range_5ghz_min = 4920; in ath5k_hw_set_capabilities()
72 caps->cap_range.range_5ghz_min = 5005; in ath5k_hw_set_capabilities()
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| /drivers/gpu/drm/msm/mdp/mdp5/ |
| D | mdp5_cfg.c | 30 .caps = MDP_CAP_SMP |
50 .caps = MDP_PIPE_CAP_HFLIP |
59 .caps = MDP_PIPE_CAP_HFLIP |
67 .caps = MDP_PIPE_CAP_HFLIP |
101 .caps = MDP_CAP_SMP |
121 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
128 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
134 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
172 .caps = MDP_CAP_SMP |
199 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
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| /drivers/crypto/marvell/ |
| D | cesa.c | 123 for (i = 0; i < cesa_dev->caps->nengines; i++) { in mv_cesa_queue_req()
138 for (i = 0; i < cesa->caps->ncipher_algs; i++) { in mv_cesa_add_algs()
139 ret = crypto_register_alg(cesa->caps->cipher_algs[i]); in mv_cesa_add_algs()
144 for (i = 0; i < cesa->caps->nahash_algs; i++) { in mv_cesa_add_algs()
145 ret = crypto_register_ahash(cesa->caps->ahash_algs[i]); in mv_cesa_add_algs()
154 crypto_unregister_ahash(cesa->caps->ahash_algs[j]); in mv_cesa_add_algs()
155 i = cesa->caps->ncipher_algs; in mv_cesa_add_algs()
159 crypto_unregister_alg(cesa->caps->cipher_algs[j]); in mv_cesa_add_algs()
168 for (i = 0; i < cesa->caps->nahash_algs; i++) in mv_cesa_remove_algs()
169 crypto_unregister_ahash(cesa->caps->ahash_algs[i]); in mv_cesa_remove_algs()
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| /drivers/mmc/core/ |
| D | host.c | 177 host->caps |= MMC_CAP_8_BIT_DATA; in mmc_of_parse()
180 host->caps |= MMC_CAP_4_BIT_DATA; in mmc_of_parse()
207 host->caps |= MMC_CAP_NONREMOVABLE; in mmc_of_parse()
212 host->caps |= MMC_CAP_NEEDS_POLL; in mmc_of_parse()
253 host->caps |= MMC_CAP_SD_HIGHSPEED; in mmc_of_parse()
255 host->caps |= MMC_CAP_MMC_HIGHSPEED; in mmc_of_parse()
257 host->caps |= MMC_CAP_UHS_SDR12; in mmc_of_parse()
259 host->caps |= MMC_CAP_UHS_SDR25; in mmc_of_parse()
261 host->caps |= MMC_CAP_UHS_SDR50; in mmc_of_parse()
263 host->caps |= MMC_CAP_UHS_SDR104; in mmc_of_parse()
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| D | sdio_irq.c | 57 !(host->caps & MMC_CAP_SDIO_IRQ)) { in process_sdio_pending_irqs()
117 period = (host->caps & MMC_CAP_SDIO_IRQ) ? in sdio_irq_thread()
160 if (!(host->caps & MMC_CAP_SDIO_IRQ)) { in sdio_irq_thread()
171 if (host->caps & MMC_CAP_SDIO_IRQ) in sdio_irq_thread()
178 if (host->caps & MMC_CAP_SDIO_IRQ) in sdio_irq_thread()
204 } else if (host->caps & MMC_CAP_SDIO_IRQ) { in sdio_card_irq_get()
223 } else if (host->caps & MMC_CAP_SDIO_IRQ) { in sdio_card_irq_put()
238 if ((card->host->caps & MMC_CAP_SDIO_IRQ) && in sdio_single_irq_set()
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| /drivers/video/fbdev/ |
| D | amba-clcd.c | 131 u32 caps; in clcdfb_set_bitfields() local
134 if (fb->panel->caps && fb->board->caps) in clcdfb_set_bitfields()
135 caps = fb->panel->caps & fb->board->caps; in clcdfb_set_bitfields()
138 caps = fb->panel->cntl & CNTL_BGR ? in clcdfb_set_bitfields()
141 caps &= ~CLCD_CAP_444; in clcdfb_set_bitfields()
146 caps &= ~CLCD_CAP_888; in clcdfb_set_bitfields()
160 caps &= CLCD_CAP_5551; in clcdfb_set_bitfields()
161 if (!caps) { in clcdfb_set_bitfields()
176 if (!(caps & (CLCD_CAP_444 | CLCD_CAP_5551 | CLCD_CAP_565))) { in clcdfb_set_bitfields()
185 if (var->green.length == 4 && caps & CLCD_CAP_444) in clcdfb_set_bitfields()
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| /drivers/clk/ingenic/ |
| D | cgu.c | 509 unsigned caps, i, num_possible; in ingenic_register_clock() local
551 caps = clk_info->type; in ingenic_register_clock()
553 if (caps & (CGU_CLK_MUX | CGU_CLK_CUSTOM)) { in ingenic_register_clock()
556 if (caps & CGU_CLK_MUX) in ingenic_register_clock()
580 if (caps & CGU_CLK_CUSTOM) { in ingenic_register_clock()
583 caps &= ~CGU_CLK_CUSTOM; in ingenic_register_clock()
585 if (caps) { in ingenic_register_clock()
587 __func__, caps); in ingenic_register_clock()
590 } else if (caps & CGU_CLK_PLL) { in ingenic_register_clock()
593 caps &= ~CGU_CLK_PLL; in ingenic_register_clock()
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| /drivers/infiniband/hw/mlx4/ |
| D | main.c | 97 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED; in check_flow_steering_support()
106 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) && in check_flow_steering_support()
108 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)); in check_flow_steering_support()
406 props->fw_ver = dev->dev->caps.fw_ver; in mlx4_ib_query_device()
412 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR) in mlx4_ib_query_device()
414 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR) in mlx4_ib_query_device()
416 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports) in mlx4_ib_query_device()
418 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT) in mlx4_ib_query_device()
420 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) in mlx4_ib_query_device()
422 if (dev->dev->caps.max_gso_sz && in mlx4_ib_query_device()
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| /drivers/ptp/ |
| D | ptp_chardev.c | 123 struct ptp_clock_caps caps; in ptp_ioctl() local
137 memset(&caps, 0, sizeof(caps)); in ptp_ioctl()
138 caps.max_adj = ptp->info->max_adj; in ptp_ioctl()
139 caps.n_alarm = ptp->info->n_alarm; in ptp_ioctl()
140 caps.n_ext_ts = ptp->info->n_ext_ts; in ptp_ioctl()
141 caps.n_per_out = ptp->info->n_per_out; in ptp_ioctl()
142 caps.pps = ptp->info->pps; in ptp_ioctl()
143 caps.n_pins = ptp->info->n_pins; in ptp_ioctl()
144 if (copy_to_user((void __user *)arg, &caps, sizeof(caps))) in ptp_ioctl()
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| D | ptp_ixp46x.c | 43 struct ptp_clock_info caps; member
141 struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps); in ptp_ixp_adjfreq()
164 struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps); in ptp_ixp_adjtime()
183 struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps); in ptp_ixp_gettime()
202 struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps); in ptp_ixp_settime()
220 struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps); in ptp_ixp_enable()
307 ixp_clock.caps = ptp_ixp_caps; in ptp_ixp_init()
309 ixp_clock.ptp_clock = ptp_clock_register(&ixp_clock.caps, NULL); in ptp_ixp_init()
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| /drivers/mmc/host/ |
| D | atmel-mci.c | 223 struct atmel_mci_caps caps; member
411 if (host->caps.has_odd_clk_div) in atmci_regs_show()
425 if (host->caps.has_cstor_reg) in atmci_regs_show()
433 if (host->caps.has_dma_conf_reg) { in atmci_regs_show()
443 if (host->caps.has_cfg_reg) { in atmci_regs_show()
754 if (!host->caps.has_rwproof) { in atmci_pdc_set_single_buf()
819 if ((!host->caps.has_rwproof) in atmci_pdc_complete()
821 if (host->caps.has_bad_data_ordering) in atmci_pdc_complete()
856 if (host->caps.has_dma_conf_reg) in atmci_dma_complete()
974 if ((!host->caps.has_rwproof) in atmci_prepare_data_pdc()
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| /drivers/hwmon/ |
| D | acpi_power_meter.c | 93 struct acpi_power_meter_capabilities caps; member
169 if (temp > resource->caps.max_avg_interval || in set_avg_interval()
170 temp < resource->caps.min_avg_interval) in set_avg_interval()
241 if (temp > resource->caps.max_cap || temp < resource->caps.min_cap) in set_cap()
331 msecs_to_jiffies(resource->caps.sampling_time)) && in update_meter()
403 val = resource->caps.min_avg_interval; in show_val()
406 val = resource->caps.max_avg_interval; in show_val()
409 val = resource->caps.min_cap * 1000; in show_val()
412 val = resource->caps.max_cap * 1000; in show_val()
415 if (resource->caps.hysteresis == UNKNOWN_HYSTERESIS) in show_val()
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| /drivers/net/wireless/ath/ath9k/ |
| D | common-init.c | 134 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) { in ath9k_cmn_init_channels_rates()
151 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) { in ath9k_cmn_init_channels_rates()
185 if (ah->caps.hw_caps & ATH9K_HW_CAP_LDPC) in ath9k_cmn_setup_ht_cap()
188 if (ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) in ath9k_cmn_setup_ht_cap()
234 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_HT)) in ath9k_cmn_reload_chainmask()
237 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) in ath9k_cmn_reload_chainmask()
240 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) in ath9k_cmn_reload_chainmask()
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| /drivers/clk/at91/ |
| D | pmc.c | 140 const struct at91_pmc_caps *caps = pmc->caps; in pmc_irq_domain_xlate() local
147 if (!(caps->available_irqs & (1 << *out_hwirq))) in pmc_irq_domain_xlate()
227 const struct at91_pmc_caps *caps) in at91_pmc_init() argument
231 if (!regbase || !virq || !caps) in at91_pmc_init()
243 pmc->caps = caps; in at91_pmc_init()
390 const struct at91_pmc_caps *caps) in of_at91_pmc_setup() argument
406 pmc = at91_pmc_init(np, regbase, virq, caps); in of_at91_pmc_setup()
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| /drivers/crypto/ |
| D | atmel-sha.c | 132 struct atmel_sha_caps caps; member
323 if (!dd->caps.has_dma) in atmel_sha_write_ctrl()
326 if (dd->caps.has_dualbuff) in atmel_sha_write_ctrl()
483 if (dd->caps.has_dma) in atmel_sha_xmit_start()
1175 if (dd->caps.has_sha224) in atmel_sha_unregister_algs()
1178 if (dd->caps.has_sha_384_512) { in atmel_sha_unregister_algs()
1194 if (dd->caps.has_sha224) { in atmel_sha_register_algs()
1200 if (dd->caps.has_sha_384_512) { in atmel_sha_register_algs()
1274 dd->caps.has_dma = 0; in atmel_sha_get_cap()
1275 dd->caps.has_dualbuff = 0; in atmel_sha_get_cap()
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| /drivers/memory/ |
| D | atmel-sdramc.c | 56 const struct at91_ramc_caps *caps; in atmel_ramc_probe() local
60 caps = match->data; in atmel_ramc_probe()
62 if (caps->has_ddrck) { in atmel_ramc_probe()
69 if (caps->has_mpddr_clk) { in atmel_ramc_probe()
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| /drivers/media/usb/tm6000/ |
| D | tm6000-cards.c | 75 struct tm6000_capabilities caps; member
93 .caps = {
120 .caps = {
146 .caps = {
174 .caps = {
213 .caps = {
239 .caps = {
264 .caps = {
291 .caps = {
321 .caps = {
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