Searched refs:cg (Results 1 – 9 of 9) sorted by relevance
| /drivers/gpio/ |
| D | gpio-crystalcove.c | 116 static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg, in crystalcove_update_irq_mask() argument
122 if (cg->set_irq_mask) in crystalcove_update_irq_mask()
123 regmap_update_bits(cg->regmap, mirqs0, mask, mask); in crystalcove_update_irq_mask()
125 regmap_update_bits(cg->regmap, mirqs0, mask, 0); in crystalcove_update_irq_mask()
128 static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio) in crystalcove_update_irq_ctrl() argument
132 regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value); in crystalcove_update_irq_ctrl()
137 struct crystalcove_gpio *cg = to_cg(chip); in crystalcove_gpio_dir_in() local
142 return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT), in crystalcove_gpio_dir_in()
149 struct crystalcove_gpio *cg = to_cg(chip); in crystalcove_gpio_dir_out() local
154 return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT), in crystalcove_gpio_dir_out()
[all …]
|
| /drivers/clk/mediatek/ |
| D | clk-gate.c | 28 struct mtk_clk_gate *cg = to_clk_gate(hw); in mtk_cg_bit_is_cleared() local
31 regmap_read(cg->regmap, cg->sta_ofs, &val); in mtk_cg_bit_is_cleared()
33 val &= BIT(cg->bit); in mtk_cg_bit_is_cleared()
40 struct mtk_clk_gate *cg = to_clk_gate(hw); in mtk_cg_bit_is_set() local
43 regmap_read(cg->regmap, cg->sta_ofs, &val); in mtk_cg_bit_is_set()
45 val &= BIT(cg->bit); in mtk_cg_bit_is_set()
52 struct mtk_clk_gate *cg = to_clk_gate(hw); in mtk_cg_set_bit() local
54 regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit)); in mtk_cg_set_bit()
59 struct mtk_clk_gate *cg = to_clk_gate(hw); in mtk_cg_clr_bit() local
61 regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit)); in mtk_cg_clr_bit()
[all …]
|
| /drivers/clk/ |
| D | clk-qoriq.c | 80 void (*init_periph)(struct clockgen *cg);
100 static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg) in cg_out() argument
102 if (cg->info.flags & CG_LITTLE_ENDIAN) in cg_out()
108 static u32 cg_in(struct clockgen *cg, u32 __iomem *reg) in cg_in() argument
112 if (cg->info.flags & CG_LITTLE_ENDIAN) in cg_in()
348 static void __init p2041_init_periph(struct clockgen *cg) in p2041_init_periph() argument
352 reg = ioread32be(&cg->guts->rcwsr[7]); in p2041_init_periph()
355 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk; in p2041_init_periph()
357 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p2041_init_periph()
360 static void __init p4080_init_periph(struct clockgen *cg) in p4080_init_periph() argument
[all …]
|
| /drivers/staging/lustre/lustre/lclient/ |
| D | lcommon_misc.c | 127 struct ccc_grouplock *cg) in cl_get_grouplock() argument
171 cg->cg_env = cl_env_get(&refcheck); in cl_get_grouplock()
172 cg->cg_io = io; in cl_get_grouplock()
173 cg->cg_lock = lock; in cl_get_grouplock()
174 cg->cg_gid = gid; in cl_get_grouplock()
175 LASSERT(cg->cg_env == env); in cl_get_grouplock()
181 void cl_put_grouplock(struct ccc_grouplock *cg) in cl_put_grouplock() argument
183 struct lu_env *env = cg->cg_env; in cl_put_grouplock()
184 struct cl_io *io = cg->cg_io; in cl_put_grouplock()
185 struct cl_lock *lock = cg->cg_lock; in cl_put_grouplock()
[all …]
|
| /drivers/staging/lustre/lustre/include/ |
| D | lclient.h | 377 struct ccc_grouplock *cg);
378 void cl_put_grouplock(struct ccc_grouplock *cg);
|
| /drivers/video/fbdev/ |
| D | simplefb.c | 54 u32 cg = green >> (16 - info->var.green.length); in simplefb_setcolreg() local
62 (cg << info->var.green.offset) | in simplefb_setcolreg()
|
| D | offb.c | 108 u32 cg = green >> (16 - info->var.green.length); in offb_setcolreg() local
116 (cg << info->var.green.offset) | in offb_setcolreg()
|
| /drivers/target/ |
| D | target_core_fabric_configfs.c | 1055 struct config_group *cg = &wwn->wwn_group; in target_fabric_drop_wwn() local
1058 for (i = 0; cg->default_groups[i]; i++) { in target_fabric_drop_wwn()
1059 df_item = &cg->default_groups[i]->cg_item; in target_fabric_drop_wwn()
1060 cg->default_groups[i] = NULL; in target_fabric_drop_wwn()
|
| /drivers/clk/tegra/ |
| D | clk-dfll.c | 294 u32 cg; member
725 force_val = (req->lut_index - td->lut_safe) * coef / td->cg; in dfll_set_frequency_request()
1264 (td->cg << DFLL_PARAMS_CG_PARAM_SHIFT) | in dfll_set_default_params()
1587 ok &= read_dt_param(td, "nvidia,cg", &td->cg); in dfll_fetch_common_params()
|