Searched refs:clk_zero (Results 1 – 4 of 4) sorted by relevance
23 DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_20nm_dphy_set_timing()28 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
23 DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_28nm_dphy_set_timing()28 if (timing->clk_zero & BIT(8)) in dsi_28nm_dphy_set_timing()
53 timing->clk_zero = clk_z + 8 - temp; in dsi_dphy_timing_calc_clk_zero()122 temp += ((timing->clk_zero >> 1) + 1) * 2 * ui; in msm_dsi_dphy_timing_calc()137 timing->clk_pre, timing->clk_post, timing->clk_zero, in msm_dsi_dphy_timing_calc()
50 u32 clk_zero; member