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Searched refs:clocks (Results 1 – 25 of 46) sorted by relevance

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/drivers/clk/bcm/
Dclk-bcm281xx.c27 .clocks = CLOCKS("ref_crystal"),
43 .clocks = CLOCKS("bbl_32k",
52 .clocks = CLOCKS("ref_crystal",
61 .clocks = CLOCKS("var_312m",
85 .clocks = CLOCKS("ref_crystal",
104 .clocks = CLOCKS("ref_crystal",
116 .clocks = CLOCKS("ref_crystal",
128 .clocks = CLOCKS("ref_crystal",
140 .clocks = CLOCKS("ref_crystal",
152 .clocks = CLOCKS("ref_crystal",
[all …]
Dclk-bcm21664.c25 .clocks = CLOCKS("ref_crystal"),
43 .clocks = CLOCKS("bbl_32k",
67 .clocks = CLOCKS("ref_crystal",
79 .clocks = CLOCKS("ref_crystal",
91 .clocks = CLOCKS("ref_crystal",
103 .clocks = CLOCKS("ref_crystal",
114 .clocks = CLOCKS("ref_32k"), /* Verify */
119 .clocks = CLOCKS("ref_32k"), /* Verify */
124 .clocks = CLOCKS("ref_32k"), /* Verify */
129 .clocks = CLOCKS("ref_32k"), /* Verify */
[all …]
Dclk-kona-setup.c535 static u32 *parent_process(const char *clocks[], in parent_process() argument
549 if (!clocks) in parent_process()
556 for (clock = clocks; *clock; clock++) in parent_process()
559 orig_count = (u32)(clock - clocks); in parent_process()
600 if (clocks[i] != BAD_CLK_NAME) { in parent_process()
601 parent_names[j] = clocks[i]; in parent_process()
613 clk_sel_setup(const char **clocks, struct bcm_clk_sel *sel, in clk_sel_setup() argument
634 parent_sel = parent_process(clocks, &parent_count, &parent_names); in clk_sel_setup()
682 return clk_sel_setup(data->clocks, &data->sel, init_data); in peri_clk_setup()
/drivers/clk/
Dclk-max-gen.c116 struct clk **clocks; in max_gen_clk_probe() local
121 clocks = devm_kzalloc(dev, sizeof(struct clk *) * num_init, GFP_KERNEL); in max_gen_clk_probe()
122 if (!clocks) in max_gen_clk_probe()
152 clocks[i] = max_gen_clk_register(dev, &max_gen_clks[i]); in max_gen_clk_probe()
153 if (IS_ERR(clocks[i])) { in max_gen_clk_probe()
154 ret = PTR_ERR(clocks[i]); in max_gen_clk_probe()
161 platform_set_drvdata(pdev, clocks); in max_gen_clk_probe()
170 of_data->clks = clocks; in max_gen_clk_probe()
Dclkdev.c27 static LIST_HEAD(clocks);
145 list_for_each_entry(p, &clocks, node) { in clk_find()
221 list_add_tail(&cl->node, &clocks); in __clkdev_add()
238 list_add_tail(&cl->node, &clocks); in clkdev_add_table()
/drivers/ata/
Dpata_atp867x.c156 unsigned char clocks = clk; in atp867x_get_active_clocks_shifted() local
163 clocks++; in atp867x_get_active_clocks_shifted()
165 switch (clocks) { in atp867x_get_active_clocks_shifted()
167 clocks = 1; in atp867x_get_active_clocks_shifted()
175 clocks = 7; /* 12 clk */ in atp867x_get_active_clocks_shifted()
179 clocks = 0; in atp867x_get_active_clocks_shifted()
184 return clocks << ATP867X_IO_PIOSPD_ACTIVE_SHIFT; in atp867x_get_active_clocks_shifted()
189 unsigned char clocks = clk; in atp867x_get_recover_clocks_shifted() local
191 switch (clocks) { in atp867x_get_recover_clocks_shifted()
193 clocks = 1; in atp867x_get_recover_clocks_shifted()
[all …]
Dpata_hpt366.c124 struct hpt_clock *clocks = ap->host->private_data; in hpt36x_find_mode() local
126 while (clocks->xfer_mode) { in hpt36x_find_mode()
127 if (clocks->xfer_mode == speed) in hpt36x_find_mode()
128 return clocks->timing; in hpt36x_find_mode()
129 clocks++; in hpt36x_find_mode()
Dpata_hpt3x2n.c44 struct hpt_clock *clocks[3]; member
105 struct hpt_clock *clocks = hpt3x2n_clocks; in hpt3x2n_find_mode() local
107 while (clocks->xfer_speed) { in hpt3x2n_find_mode()
108 if (clocks->xfer_speed == speed) in hpt3x2n_find_mode()
109 return clocks->timing; in hpt3x2n_find_mode()
110 clocks++; in hpt3x2n_find_mode()
Dpata_hpt37x.c38 struct hpt_clock const *clocks[4]; member
212 struct hpt_clock *clocks = ap->host->private_data; in hpt37x_find_mode() local
214 while (clocks->xfer_speed) { in hpt37x_find_mode()
215 if (clocks->xfer_speed == speed) in hpt37x_find_mode()
216 return clocks->timing; in hpt37x_find_mode()
217 clocks++; in hpt37x_find_mode()
974 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) { in hpt37x_init_one()
1023 private_data = (void *)chip_table->clocks[clock_slot]; in hpt37x_init_one()
/drivers/media/platform/exynos4-is/
Dfimc-is.c71 if (IS_ERR(is->clocks[i])) in fimc_is_put_clocks()
73 clk_put(is->clocks[i]); in fimc_is_put_clocks()
74 is->clocks[i] = ERR_PTR(-EINVAL); in fimc_is_put_clocks()
83 is->clocks[i] = ERR_PTR(-EINVAL); in fimc_is_get_clocks()
86 is->clocks[i] = clk_get(&is->pdev->dev, fimc_is_clocks[i]); in fimc_is_get_clocks()
87 if (IS_ERR(is->clocks[i])) { in fimc_is_get_clocks()
88 ret = PTR_ERR(is->clocks[i]); in fimc_is_get_clocks()
105 ret = clk_set_parent(is->clocks[ISS_CLK_ACLK200], in fimc_is_setup_clocks()
106 is->clocks[ISS_CLK_ACLK200_DIV]); in fimc_is_setup_clocks()
110 ret = clk_set_parent(is->clocks[ISS_CLK_ACLK400MCUISP], in fimc_is_setup_clocks()
[all …]
/drivers/clk/ingenic/
Dcgu.c527 cgu->clocks.clks[idx] = clk; in ingenic_register_clock()
565 parent = cgu->clocks.clks[clk_info->parents[i]]; in ingenic_register_clock()
576 parent = cgu->clocks.clks[clk_info->parents[0]]; in ingenic_register_clock()
638 cgu->clocks.clks[idx] = clk; in ingenic_register_clock()
663 cgu->clocks.clk_num = num_clocks; in ingenic_cgu_new()
680 cgu->clocks.clks = kcalloc(cgu->clocks.clk_num, sizeof(struct clk *), in ingenic_cgu_register_clocks()
682 if (!cgu->clocks.clks) { in ingenic_cgu_register_clocks()
687 for (i = 0; i < cgu->clocks.clk_num; i++) { in ingenic_cgu_register_clocks()
694 &cgu->clocks); in ingenic_cgu_register_clocks()
701 for (i = 0; i < cgu->clocks.clk_num; i++) { in ingenic_cgu_register_clocks()
[all …]
Dcgu.h180 struct clk_onecell_data clocks; member
/drivers/mfd/
Dasic3.c87 struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)]; member
665 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); in ds1wm_enable()
666 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); in ds1wm_enable()
667 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); in ds1wm_enable()
691 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); in ds1wm_disable()
692 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); in ds1wm_disable()
693 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); in ds1wm_disable()
755 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); in asic3_mmc_enable()
759 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); in asic3_mmc_enable()
766 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]); in asic3_mmc_enable()
[all …]
/drivers/staging/clocking-wizard/
Ddt-binding.txt13 - clocks: Handle to input clock
15 - clock-output-names: Names for the output clocks
26 clocks = <&clkc 15>, <&clkc 15>;
/drivers/gpu/drm/exynos/
Dexynos_drm_fimc.c162 struct clk *clocks[FIMC_CLKS_MAX]; member
1581 if (IS_ERR(ctx->clocks[i])) in fimc_put_clocks()
1583 clk_put(ctx->clocks[i]); in fimc_put_clocks()
1584 ctx->clocks[i] = ERR_PTR(-EINVAL); in fimc_put_clocks()
1595 ctx->clocks[i] = ERR_PTR(-EINVAL); in fimc_setup_clocks()
1603 ctx->clocks[i] = clk_get(dev, fimc_clock_names[i]); in fimc_setup_clocks()
1604 if (IS_ERR(ctx->clocks[i])) { in fimc_setup_clocks()
1607 ret = PTR_ERR(ctx->clocks[i]); in fimc_setup_clocks()
1615 if (!IS_ERR(ctx->clocks[FIMC_CLK_PARENT])) { in fimc_setup_clocks()
1616 ret = clk_set_parent(ctx->clocks[FIMC_CLK_MUX], in fimc_setup_clocks()
[all …]
/drivers/staging/media/davinci_vpfe/
Dvpfe_mc_capture.c235 if (vpfe_cfg->clocks[i] == NULL) { in vpfe_enable_clock()
238 vpfe_cfg->clocks[i]); in vpfe_enable_clock()
243 clk_get(vpfe_dev->pdev, vpfe_cfg->clocks[i]); in vpfe_enable_clock()
247 vpfe_cfg->clocks[i]); in vpfe_enable_clock()
254 vpfe_cfg->clocks[i]); in vpfe_enable_clock()
259 vpfe_cfg->clocks[i]); in vpfe_enable_clock()
Dvpfe.h83 char *clocks[]; member
/drivers/clk/ti/
Dclk.c217 struct device_node *clocks; in omap2_clk_provider_init() local
221 clocks = of_get_child_by_name(parent, "clocks"); in omap2_clk_provider_init()
222 if (!clocks) { in omap2_clk_provider_init()
228 clocks_node_ptr[index] = clocks; in omap2_clk_provider_init()
/drivers/ptp/
DKconfig14 synchronize distributed clocks over Ethernet networks. The
21 This driver adds support for PTP clocks as character
56 comment "Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks."
/drivers/gpu/drm/radeon/
Dbtc_dpm.c1211 static u32 btc_find_valid_clock(struct radeon_clock_array *clocks, in btc_find_valid_clock() argument
1216 if ((clocks == NULL) || (clocks->count == 0)) in btc_find_valid_clock()
1219 for (i = 0; i < clocks->count; i++) { in btc_find_valid_clock()
1220 if (clocks->values[i] >= requested_clock) in btc_find_valid_clock()
1221 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock; in btc_find_valid_clock()
1224 return (clocks->values[clocks->count - 1] < max_clock) ? in btc_find_valid_clock()
1225 clocks->values[clocks->count - 1] : max_clock; in btc_find_valid_clock()
/drivers/staging/board/
Dboard.h17 const struct board_staging_clk *clocks; member
Darmadillo800eva.c92 .clocks = lcdc0_clocks,
/drivers/media/pci/cx23885/
Dcx23888-ir.c316 u64 clocks; in ns_to_pulse_clocks() local
318 clocks = CX23888_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */ in ns_to_pulse_clocks()
319 rem = do_div(clocks, 1000); /* /1000 = cycles */ in ns_to_pulse_clocks()
321 clocks++; in ns_to_pulse_clocks()
322 return clocks; in ns_to_pulse_clocks()
/drivers/staging/iio/trigger/
DKconfig13 clocks as IIO triggers.
/drivers/media/i2c/cx25840/
Dcx25840-ir.c308 u64 clocks; in ns_to_pulse_clocks() local
310 clocks = CX25840_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */ in ns_to_pulse_clocks()
311 rem = do_div(clocks, 1000); /* /1000 = cycles */ in ns_to_pulse_clocks()
313 clocks++; in ns_to_pulse_clocks()
314 return clocks; in ns_to_pulse_clocks()

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