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Searched refs:con1 (Results 1 – 4 of 4) sorted by relevance

/drivers/iio/adc/
Dexynos_adc.c189 u32 con1; in exynos_adc_v1_init_hw() local
195 con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN; in exynos_adc_v1_init_hw()
198 con1 |= ADC_V1_CON_RES; in exynos_adc_v1_init_hw()
199 writel(con1, ADC_V1_CON(info->regs)); in exynos_adc_v1_init_hw()
222 u32 con1; in exynos_adc_v1_start_conv() local
226 con1 = readl(ADC_V1_CON(info->regs)); in exynos_adc_v1_start_conv()
227 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); in exynos_adc_v1_start_conv()
245 u32 con1; in exynos_adc_s3c2416_start_conv() local
248 con1 = readl(ADC_V1_CON(info->regs)); in exynos_adc_s3c2416_start_conv()
249 con1 |= ADC_S3C2416_CON_RES_SEL; in exynos_adc_s3c2416_start_conv()
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/drivers/clk/samsung/
Dclk-pll.c401 u32 con0, con1; in samsung_pll45xx_set_rate() local
413 con1 = __raw_readl(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
415 if (!(samsung_pll45xx_mp_change(con0, con1, rate))) { in samsung_pll45xx_set_rate()
433 con1 = __raw_readl(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
434 con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT); in samsung_pll45xx_set_rate()
435 con1 |= (rate->afc << PLL45XX_AFC_SHIFT); in samsung_pll45xx_set_rate()
450 __raw_writel(con1, pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
552 u32 con0, con1, lock; in samsung_pll46xx_set_rate() local
564 con1 = __raw_readl(pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
566 if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) { in samsung_pll46xx_set_rate()
[all …]
/drivers/clk/mediatek/
Dclk-pll.c93 u32 con1, val; in mtk_pll_set_rate_regs() local
115 con1 = readl(pll->base_addr + REG_CON1); in mtk_pll_set_rate_regs()
118 con1 |= CON0_PCW_CHG; in mtk_pll_set_rate_regs()
120 writel(con1, pll->base_addr + REG_CON1); in mtk_pll_set_rate_regs()
122 writel(con1 + 1, pll->tuner_addr); in mtk_pll_set_rate_regs()
/drivers/media/dvb-frontends/
Ditd1000.c134 u8 con1 = itd1000_read_reg(state, CON1) & 0xfd; in itd1000_set_lpf_bw() local
142 itd1000_write_reg(state, CON1, con1 | (1 << 1)); in itd1000_set_lpf_bw()
153 itd1000_write_reg(state, CON1, con1 | (0 << 1)); in itd1000_set_lpf_bw()