Home
last modified time | relevance | path

Searched refs:crtc_w (Results 1 – 25 of 38) sorted by relevance

12

/drivers/gpu/drm/imx/
Dipuv3-plane.c109 unsigned int crtc_w, unsigned int crtc_h, in ipu_plane_mode_set() argument
117 if (src_w != crtc_w || src_h != crtc_h) in ipu_plane_mode_set()
122 if (-crtc_x > crtc_w) in ipu_plane_mode_set()
126 crtc_w -= -crtc_x; in ipu_plane_mode_set()
137 if (crtc_x + crtc_w > mode->hdisplay) { in ipu_plane_mode_set()
140 crtc_w = mode->hdisplay - crtc_x; in ipu_plane_mode_set()
141 src_w = crtc_w; in ipu_plane_mode_set()
150 if (crtc_w < 13 && (ipu_plane->dp_flow != IPU_DP_FLOW_SYNC_FG)) in ipu_plane_mode_set()
203 ret = ipu_dmfc_init_channel(ipu_plane->dmfc, crtc_w); in ipu_plane_mode_set()
210 calc_bandwidth(crtc_w, crtc_h, in ipu_plane_mode_set()
[all …]
Dipuv3-plane.h43 unsigned int crtc_w, unsigned int crtc_h,
/drivers/gpu/drm/atmel-hlcdc/
Datmel_hlcdc_plane.c45 unsigned int crtc_w; member
269 (state->crtc_w - 1) | in atmel_hlcdc_plane_update_pos_and_size()
287 if (state->crtc_w != state->src_w || state->crtc_h != state->src_h) { in atmel_hlcdc_plane_update_pos_and_size()
290 if (state->crtc_w != state->src_w) { in atmel_hlcdc_plane_update_pos_and_size()
296 if (state->crtc_w < state->src_w) in atmel_hlcdc_plane_update_pos_and_size()
304 state->crtc_w; in atmel_hlcdc_plane_update_pos_and_size()
306 max_memsize = ((factor * state->crtc_w) + (256 * 4)) / in atmel_hlcdc_plane_update_pos_and_size()
481 if (ovl_state->crtc_h * ovl_state->crtc_w < disc_h * disc_w) in atmel_hlcdc_plane_prepare_disc_area()
487 disc_w = ovl_state->crtc_w; in atmel_hlcdc_plane_prepare_disc_area()
573 state->crtc_w = s->crtc_w; in atmel_hlcdc_plane_atomic_check()
[all …]
/drivers/gpu/drm/msm/mdp/mdp4/
Dmdp4_plane.c57 unsigned int crtc_w, unsigned int crtc_h,
145 state->crtc_w, state->crtc_h, in mdp4_plane_atomic_update()
218 unsigned int crtc_w, unsigned int crtc_h, in mdp4_plane_mode_set() argument
247 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); in mdp4_plane_mode_set()
251 if (src_w > (crtc_w * DOWN_SCALE_MAX)) { in mdp4_plane_mode_set()
261 if (crtc_w > (src_w * UP_SCALE_MAX)) { in mdp4_plane_mode_set()
271 if (src_w != crtc_w) { in mdp4_plane_mode_set()
276 if (crtc_w > src_w) in mdp4_plane_mode_set()
278 else if (crtc_w <= (src_w / 4)) in mdp4_plane_mode_set()
283 src_w, crtc_w); in mdp4_plane_mode_set()
[all …]
/drivers/gpu/drm/i915/
Dintel_sprite.c184 unsigned int crtc_w, unsigned int crtc_h, in skl_update_plane() argument
217 src_w != crtc_w || src_h != crtc_h); in skl_update_plane()
227 crtc_w--; in skl_update_plane()
275 ((crtc_w + 1) << 16)|(crtc_h + 1)); in skl_update_plane()
347 unsigned int crtc_w, unsigned int crtc_h, in vlv_update_plane() argument
420 crtc_w--; in vlv_update_plane()
461 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); in vlv_update_plane()
487 unsigned int crtc_w, unsigned int crtc_h, in ivb_update_plane() argument
546 src_w != crtc_w || src_h != crtc_h); in ivb_update_plane()
551 crtc_w--; in ivb_update_plane()
[all …]
Dintel_atomic_plane.c146 intel_state->dst.x2 = state->crtc_x + state->crtc_w; in intel_plane_atomic_check()
/drivers/gpu/drm/exynos/
Dexynos_drm_plane.c63 unsigned int crtc_w, unsigned int crtc_h, in exynos_plane_mode_set() argument
72 actual_w = exynos_plane_get_size(crtc_x, crtc_w, mode->hdisplay); in exynos_plane_mode_set()
88 exynos_plane->h_ratio = (src_w << 16) / crtc_w; in exynos_plane_mode_set()
100 exynos_plane->crtc_w = actual_w; in exynos_plane_mode_set()
105 exynos_plane->crtc_w, exynos_plane->crtc_h); in exynos_plane_mode_set()
160 state->crtc_w, state->crtc_h, in exynos_plane_atomic_update()
Dexynos5433_drm_decon.c277 val = COORDINATE_X(plane->crtc_x + plane->crtc_w - 1) | in decon_update_plane()
295 val = BIT_VAL(pitch - plane->crtc_w * bpp, 27, 14) in decon_update_plane()
296 | BIT_VAL(plane->crtc_w * bpp, 13, 0); in decon_update_plane()
298 val = BIT_VAL(pitch - plane->crtc_w * bpp, 29, 15) in decon_update_plane()
299 | BIT_VAL(plane->crtc_w * bpp, 14, 0); in decon_update_plane()
Dexynos_drm_fimd.c671 plane->crtc_w, plane->crtc_h); in fimd_update_plane()
674 buf_offsize = pitch - (plane->crtc_w * bpp); in fimd_update_plane()
675 line_size = plane->crtc_w * bpp; in fimd_update_plane()
689 last_x = plane->crtc_x + plane->crtc_w; in fimd_update_plane()
709 val = plane->crtc_w * plane->crtc_h; in fimd_update_plane()
Dexynos7_drm_decon.c442 plane->crtc_w, plane->crtc_h); in decon_update_plane()
448 if ((plane->crtc_x + plane->crtc_w) > mode->hdisplay) in decon_update_plane()
449 plane->crtc_x = mode->hdisplay - plane->crtc_w; in decon_update_plane()
457 last_x = plane->crtc_x + plane->crtc_w; in decon_update_plane()
Dexynos_drm_drv.h73 unsigned int crtc_w; member
/drivers/gpu/drm/virtio/
Dvirtgpu_plane.c78 cpu_to_le32(plane->state->crtc_w), in virtio_gpu_plane_atomic_update()
87 plane->state->crtc_w, plane->state->crtc_h, in virtio_gpu_plane_atomic_update()
90 plane->state->crtc_w, in virtio_gpu_plane_atomic_update()
97 plane->state->crtc_w, in virtio_gpu_plane_atomic_update()
/drivers/gpu/drm/shmobile/
Dshmob_drm_plane.c39 unsigned int crtc_w; member
139 (splane->crtc_w << LDBBSSZR_BHSS_SHIFT)); in __shmob_drm_plane_setup()
178 unsigned int crtc_w, unsigned int crtc_h, in shmob_drm_plane_update() argument
193 if (src_w >> 16 != crtc_w || src_h >> 16 != crtc_h) { in shmob_drm_plane_update()
204 splane->crtc_w = crtc_w; in shmob_drm_plane_update()
/drivers/gpu/drm/nouveau/dispnv04/
Doverlay.c95 unsigned int crtc_w, unsigned int crtc_h, in nv10_update_plane() argument
123 if (crtc_w < (src_w >> 1) || crtc_h < (src_h >> 1)) in nv10_update_plane()
126 if (crtc_w < (src_w >> 3) || crtc_h < (src_h >> 3)) in nv10_update_plane()
143 nvif_wr32(dev, NV_PVIDEO_DS_DX(flip), (src_w << 20) / crtc_w); in nv10_update_plane()
146 nvif_wr32(dev, NV_PVIDEO_SIZE_OUT(flip), crtc_h << 16 | crtc_w); in nv10_update_plane()
346 unsigned int crtc_w, unsigned int crtc_h, in nv04_update_plane() argument
374 if (crtc_w < src_w || crtc_h < src_h) in nv04_update_plane()
394 nvif_wr32(dev, NV_PVIDEO_WINDOW_SIZE, crtc_h << 16 | crtc_w); in nv04_update_plane()
396 …(uint32_t)(((src_h - 1) << 11) / (crtc_h - 1)) << 16 | (uint32_t)(((src_w - 1) << 11) / (crtc_w - … in nv04_update_plane()
/drivers/gpu/drm/vc4/
Dvc4_plane.c157 int crtc_w = state->crtc_w; in vc4_plane_mode_set() local
160 if (state->crtc_w << 16 != state->src_w || in vc4_plane_mode_set()
172 crtc_w += crtc_x; in vc4_plane_mode_set()
204 VC4_SET_FIELD(crtc_w, SCALER_POS2_WIDTH) | in vc4_plane_mode_set()
/drivers/gpu/drm/
Ddrm_plane_helper.c227 unsigned int crtc_w, unsigned int crtc_h, in drm_primary_helper_update() argument
247 .x2 = crtc_x + crtc_w, in drm_primary_helper_update()
521 unsigned int crtc_w, unsigned int crtc_h, in drm_plane_helper_update() argument
544 plane_state->crtc_w = crtc_w; in drm_plane_helper_update()
Ddrm_atomic.c599 state->crtc_w = val; in drm_atomic_plane_set_property()
646 *val = state->crtc_w; in drm_atomic_plane_get_property()
731 if (state->crtc_w > INT_MAX || in drm_atomic_plane_check()
732 state->crtc_x > INT_MAX - (int32_t) state->crtc_w || in drm_atomic_plane_check()
736 state->crtc_w, state->crtc_h, in drm_atomic_plane_check()
Ddrm_atomic_helper.c1458 unsigned int crtc_w, unsigned int crtc_h, in drm_atomic_helper_update_plane() argument
1485 plane_state->crtc_w = crtc_w; in drm_atomic_helper_update_plane()
1609 plane_state->crtc_w = 0; in __drm_atomic_helper_disable_plane()
1797 primary_state->crtc_w = hdisplay; in __drm_atomic_helper_set_config()
/drivers/gpu/drm/msm/mdp/mdp5/
Dmdp5_plane.c41 unsigned int crtc_w, unsigned int crtc_h,
302 (((state->src_w >> 16) != state->crtc_w) || in mdp5_plane_atomic_check()
307 state->crtc_w, state->crtc_h); in mdp5_plane_atomic_check()
367 state->crtc_w, state->crtc_h, in mdp5_plane_atomic_update()
668 unsigned int crtc_w, unsigned int crtc_h, in mdp5_plane_mode_set() argument
705 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); in mdp5_plane_mode_set()
724 ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, phasex_step); in mdp5_plane_mode_set()
733 calc_pixel_ext(format, src_w, crtc_w, phasex_step, in mdp5_plane_mode_set()
742 config |= get_scale_config(format, src_w, crtc_w, true); in mdp5_plane_mode_set()
764 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) | in mdp5_plane_mode_set()
/drivers/gpu/drm/omapdrm/
Domap_plane.c101 win.crtc_w = state->crtc_w; in omap_plane_atomic_update()
174 if (state->crtc_x + state->crtc_w > crtc_state->adjusted_mode.hdisplay) in omap_plane_atomic_check()
/drivers/gpu/drm/rockchip/
Drockchip_drm_vop.c791 int crtc_y, unsigned int crtc_w, in vop_update_plane_event() argument
823 .x2 = crtc_x + crtc_w, in vop_update_plane_event()
991 unsigned int crtc_w, unsigned int crtc_h, in vop_update_plane() argument
995 return vop_update_plane_event(plane, crtc, fb, crtc_x, crtc_y, crtc_w, in vop_update_plane()
1003 unsigned int crtc_w, crtc_h; in vop_update_primary_plane() local
1005 crtc_w = crtc->primary->fb->width - crtc->x; in vop_update_primary_plane()
1009 0, 0, crtc_w, crtc_h, crtc->x << 16, in vop_update_primary_plane()
1010 crtc->y << 16, crtc_w << 16, in vop_update_primary_plane()
/drivers/gpu/drm/tegra/
Ddc.c579 window.dst.w = plane->state->crtc_w; in tegra_plane_atomic_update()
689 if ((state->src_w >> 16 != state->crtc_w) || in tegra_cursor_atomic_check()
697 if (state->crtc_w != 32 && state->crtc_w != 64 && in tegra_cursor_atomic_check()
698 state->crtc_w != 128 && state->crtc_w != 256) in tegra_cursor_atomic_check()
720 switch (state->crtc_w) { in tegra_cursor_atomic_update()
738 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w, in tegra_cursor_atomic_update()
/drivers/gpu/drm/sti/
Dsti_vid.c53 int dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x); in sti_vid_commit()
/drivers/gpu/drm/rcar-du/
Drcar_du_plane.c210 rcar_du_plane_write(rgrp, index, PnDSXR, plane->plane.state->crtc_w); in __rcar_du_plane_setup()
246 if (state->src_w >> 16 != state->crtc_w || in rcar_du_plane_atomic_check()
/drivers/gpu/drm/fsl-dcu/
Dfsl_dcu_drm_plane.c128 DCU_LAYER_WIDTH(state->crtc_w)); in fsl_dcu_drm_plane_atomic_update()

12