Searched refs:csel (Results 1 – 4 of 4) sorted by relevance
44 unsigned int csel; /* system clock divider */ member62 unsigned long csel, min_cclk; in bfin_init_tables() local75 csel = ((bfin_read_PLL_DIV() & CSEL) >> 4); in bfin_init_tables()77 csel = bfin_read32(CGU0_DIV) & 0x1F; in bfin_init_tables()80 for (index = 0; (cclk >> index) >= min_cclk && csel <= 3 && index < 3; index++, csel++) { in bfin_init_tables()83 dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */ in bfin_init_tables()85 dpm_state_table[index].csel = csel; in bfin_init_tables()91 dpm_state_table[index].csel, in bfin_init_tables()148 plldiv = (bfin_read_PLL_DIV() & SSEL) | dpm_state_table[index].csel; in bfin_target()
48 int csel; member161 (state->csel << 1) | in smrt_set()358 state->deci = 0; state->csel = 0; state->rsel = 0; in smrt_info_get()360 state->deci = 0; state->csel = 0; state->rsel = 1; in smrt_info_get()362 state->deci = 0; state->csel = 1; state->rsel = 0; in smrt_info_get()364 state->deci = 0; state->csel = 1; state->rsel = 1; in smrt_info_get()366 state->deci = 1; state->csel = 0; state->rsel = 0; in smrt_info_get()368 state->deci = 1; state->csel = 0; state->rsel = 1; in smrt_info_get()370 state->deci = 1; state->csel = 1; state->rsel = 0; in smrt_info_get()372 state->deci = 1; state->csel = 1; state->rsel = 1; in smrt_info_get()[all …]
55 int csel; member344 priv->csel = device; in mpc52xx_ata_apply_timings()436 if (device != priv->csel) in mpc52xx_ata_dev_select()750 priv->csel = -1; in mpc52xx_ata_probe()
479 int csel = cdata->chansel >> (phy->id * in s3c24xx_dma_start_next_sg() local482 csel &= S3C24XX_CHANSEL_REQ_MASK; in s3c24xx_dma_start_next_sg()483 dcon |= csel << S3C24XX_DCON_HWSRC_SHIFT; in s3c24xx_dma_start_next_sg()