Searched refs:ctl18 (Results 1 – 2 of 2) sorted by relevance
90 u32 ctl18; /* DMA control 18 */ member
97 ACCESS_ONCE(ads->ctl18) = 0; in ar9003_set_txdesc()147 ACCESS_ONCE(ads->ctl18) = set11nRateFlags(i->rates, 0) in ar9003_set_txdesc()