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Searched refs:cx_set (Results 1 – 22 of 22) sorted by relevance

/drivers/media/pci/cx23885/
Dcx23885-cards.c1204 cx_set(GP0_IO, 0x00070007); in tbs_card_init()
1211 cx_set(GP0_IO, in tbs_card_init()
1215 cx_set(GP0_IO, 7); in tbs_card_init()
1275 cx_set(GP0_IO, bitmask); in cx23885_tuner_callback()
1286 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ in cx23885_gpio_setup()
1293 cx_set(GP0_IO, 0x00050000); in cx23885_gpio_setup()
1298 cx_set(GP0_IO, 0x00050005); in cx23885_gpio_setup()
1303 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */ in cx23885_gpio_setup()
1341 cx_set(GP0_IO, 0x00050000); in cx23885_gpio_setup()
1345 cx_set(GP0_IO, 0x00050005); in cx23885_gpio_setup()
[all …]
Dcx23885-vbi.c113 cx_set(VID_A_INT_MSK, 0x000022); in cx23885_start_vbi_dma()
116 cx_set(DEV_CNTRL2, (1<<5)); in cx23885_start_vbi_dma()
117 cx_set(VID_A_DMA_CTL, 0x22); /* FIFO and RISC enable */ in cx23885_start_vbi_dma()
Dcx23885-alsa.c201 cx_set(PCI_INT_MSK, chip->dev->pci_irqmask | PCI_MSK_AUD_INT); in cx23885_start_audio_dma()
204 cx_set(DEV_CNTRL2, (1<<5)); /* Enables Risc Processor */ in cx23885_start_audio_dma()
205 cx_set(AUD_INT_DMA_CTL, 0x11); /* audio downstream FIFO and in cx23885_start_audio_dma()
Dcx23885-core.c318 cx_set(PCI_INT_MSK, mask); in cx23885_irq_add_enable()
331 cx_set(PCI_INT_MSK, v); in cx23885_irq_enable()
1409 cx_set(port->reg_ts_int_msk, port->ts_int_msk_val); in cx23885_start_dma()
1410 cx_set(port->reg_dma_ctl, port->dma_ctl_val); in cx23885_start_dma()
1418 cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */ in cx23885_start_dma()
1880 cx_set(GP0_IO, mask & 0x7); in cx23885_gpio_set()
1887 cx_set(MC417_RWD, (mask & 0x0007fff8) >> 3); in cx23885_gpio_set()
1936 cx_set(GP0_IO, (mask & 0x7) << 16); in cx23885_gpio_enable()
1952 cx_set(MC417_OEN, (mask & 0x7fff8) >> 3); in cx23885_gpio_enable()
Dcx23885-video.c309 cx_set(VID_A_INT_MSK, 0x000011); in cx23885_start_video_dma()
312 cx_set(DEV_CNTRL2, (1<<5)); in cx23885_start_video_dma()
313 cx_set(VID_A_DMA_CTL, 0x11); /* FIFO and RISC enable */ in cx23885_start_video_dma()
Dcimax2.c172 cx_set(MC417_RWD, NETUP_CTRL_OFF); in netup_ci_get_mem()
Dcx23885.h502 #define cx_set(reg, bit) cx_andor((reg), (bit), (bit)) macro
Dcx23885-dvb.c702 cx_set(MC417_RWD, SP2_CTRL_OFF); in cx23885_sp2_ci_ctrl()
934 cx_set(MC417_OEN, ALT_DATA); in netup_altera_fpga_rw()
963 cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS); in netup_altera_fpga_rw()
/drivers/media/pci/cx88/
Dcx88-vbi.c65 cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_VIDINT); in cx8800_start_vbi_dma()
66 cx_set(MO_VID_INTMSK, 0x0f0088); in cx8800_start_vbi_dma()
69 cx_set(VID_CAPTURE_CONTROL,0x18); in cx8800_start_vbi_dma()
72 cx_set(MO_DEV_CNTRL2, (1<<5)); in cx8800_start_vbi_dma()
73 cx_set(MO_VID_DMACNTRL, 0x88); in cx8800_start_vbi_dma()
Dcx88-dvb.c399 cx_set(MO_GP0_IO, 8); in lgdt330x_pll_rf_set()
492 cx_set(MO_GP0_IO, 0x6040); in tevii_dvbs_set_voltage()
498 cx_set(MO_GP0_IO, 0x20); in tevii_dvbs_set_voltage()
908 cx_set(MO_GP0_IO, 0x0800); in samsung_smt_7020_set_tone()
912 cx_set(MO_GP0_IO, 0x08); in samsung_smt_7020_set_tone()
937 cx_set(MO_GP0_IO, 0x8000); in samsung_smt_7020_set_voltage()
1237 cx_set(MO_GP0_IO, 1); in dvb_register()
1258 cx_set(MO_GP0_IO, 9); in dvb_register()
1276 cx_set(MO_GP0_IO, 1); in dvb_register()
1297 cx_set(MO_GP0_IO, 1); in dvb_register()
[all …]
Dcx88-cards.c2905 cx_set(MO_GP0_IO, 0x008989FF); in hauppauge_eeprom()
2978 cx_set(MO_GP0_IO, 0x00001000); in cx88_dvico_xc2028_callback()
2981 cx_set(MO_GP0_IO, 0x00000010); in cx88_dvico_xc2028_callback()
2987 cx_set(MO_GP0_IO, 0x101010); in cx88_dvico_xc2028_callback()
3034 cx_set(MO_GP1_IO, 0x1010); in cx88_xc3028_winfast1800h_callback()
3038 cx_set(MO_GP1_IO, 0x10); in cx88_xc3028_winfast1800h_callback()
3051 cx_set(MO_GP1_IO, 0x1010); in cx88_xc4000_winfast2000h_plus_callback()
3055 cx_set(MO_GP1_IO, 0x10); in cx88_xc4000_winfast2000h_plus_callback()
3216 cx_set(MO_GP0_IO, 0x00000010); in cx88_xc5000_tuner_callback()
3309 cx_set(MO_GP0_IO, 0x00000088); /* 702 out of reset */ in cx88_card_setup_pre_i2c()
[all …]
Dcx88-video.c315 cx_set(MO_AFECFG_IO, 0x00000001); in cx88_video_mux()
316 cx_set(MO_INPUT_FORMAT, 0x00010010); in cx88_video_mux()
317 cx_set(MO_FILTER_EVEN, 0x00002020); in cx88_video_mux()
318 cx_set(MO_FILTER_ODD, 0x00002020); in cx88_video_mux()
376 cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_VIDINT); in start_video_dma()
385 cx_set(MO_VID_INTMSK, 0x0f0011); in start_video_dma()
388 cx_set(VID_CAPTURE_CONTROL,0x06); in start_video_dma()
391 cx_set(MO_DEV_CNTRL2, (1<<5)); in start_video_dma()
392 cx_set(MO_VID_DMACNTRL, 0x11); /* Planar Y and packed FIFO and RISC enable */ in start_video_dma()
1346 cx_set(MO_PCI_INTMSK, core->pci_irqmask); in cx8800_initdev()
[all …]
Dcx88-mpeg.c180 cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_TSINT); in cx8802_start_dma()
181 cx_set(MO_TS_INTMSK, 0x1f0011); in cx8802_start_dma()
184 cx_set(MO_DEV_CNTRL2, (1<<5)); in cx8802_start_dma()
185 cx_set(MO_TS_DMACNTRL, 0x11); in cx8802_start_dma()
423 cx_set(MO_PCI_INTMSK, core->pci_irqmask); in cx8802_init_common()
Dcx88-alsa.c169 cx_set(MO_PCI_INTMSK, chip->core->pci_irqmask | PCI_INT_AUDINT); in _cx88_start_audio_dma()
172 cx_set(MO_DEV_CNTRL2, (1<<5)); /* Enables Risc Processor */ in _cx88_start_audio_dma()
173 cx_set(MO_AUD_DMACNTRL, 0x11); /* audio downstream FIFO and RISC enable */ in _cx88_start_audio_dma()
Dcx88-blackbird.c1074 cx_set(MO_GP0_IO, 0x00000080); in cx8802_blackbird_advise_acquire()
1078 cx_set(MO_GP0_IO, 0x00000080); in cx8802_blackbird_advise_acquire()
1081 cx_set(MO_GP0_IO, 0x00000004); in cx8802_blackbird_advise_acquire()
Dcx88.h600 #define cx_set(reg,bit) cx_andor((reg),(bit),(bit)) macro
Dcx88-tvaudio.c149 cx_set(AUD_CTL, EN_I2SOUT_ENABLE); in set_audio_finish()
/drivers/media/pci/cx25821/
Dcx25821-video-upstream.c258 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) & ~(1 << sram_ch->irq_bit)); in cx25821_stop_upstream_video()
579 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit)); in cx25821_start_video_dma_upstream()
593 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN); in cx25821_start_video_dma_upstream()
Dcx25821-video.c89 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << channel->i)); in cx25821_start_video_dma()
90 cx_set(channel->int_msk, 0x11); in cx25821_start_video_dma()
789 cx_set(PCI_INT_MSK, 0xff); in cx25821_video_register()
Dcx25821-audio-upstream.c598 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit)); in cx25821_start_audio_dma_upstream()
612 cx_set(sram_ch->dma_ctl, tmp | sram_ch->fld_aud_risc_en); in cx25821_start_audio_dma_upstream()
Dcx25821-alsa.c274 cx_set(PCI_INT_MSK, chip->dev->pci_irqmask | PCI_MSK_AUD_INT); in _cx25821_start_audio_dma()
278 cx_set(AUD_INT_DMA_CTL, tmp | in _cx25821_start_audio_dma()
Dcx25821.h377 #define cx_set(reg, bit) cx_andor((reg), (bit), (bit)) macro