1 /* 2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called COPYING. 16 */ 17 #ifndef _IOAT_HW_H_ 18 #define _IOAT_HW_H_ 19 20 /* PCI Configuration Space Values */ 21 #define IOAT_MMIO_BAR 0 22 23 /* CB device ID's */ 24 #define PCI_DEVICE_ID_INTEL_IOAT_IVB0 0x0e20 25 #define PCI_DEVICE_ID_INTEL_IOAT_IVB1 0x0e21 26 #define PCI_DEVICE_ID_INTEL_IOAT_IVB2 0x0e22 27 #define PCI_DEVICE_ID_INTEL_IOAT_IVB3 0x0e23 28 #define PCI_DEVICE_ID_INTEL_IOAT_IVB4 0x0e24 29 #define PCI_DEVICE_ID_INTEL_IOAT_IVB5 0x0e25 30 #define PCI_DEVICE_ID_INTEL_IOAT_IVB6 0x0e26 31 #define PCI_DEVICE_ID_INTEL_IOAT_IVB7 0x0e27 32 #define PCI_DEVICE_ID_INTEL_IOAT_IVB8 0x0e2e 33 #define PCI_DEVICE_ID_INTEL_IOAT_IVB9 0x0e2f 34 35 #define PCI_DEVICE_ID_INTEL_IOAT_HSW0 0x2f20 36 #define PCI_DEVICE_ID_INTEL_IOAT_HSW1 0x2f21 37 #define PCI_DEVICE_ID_INTEL_IOAT_HSW2 0x2f22 38 #define PCI_DEVICE_ID_INTEL_IOAT_HSW3 0x2f23 39 #define PCI_DEVICE_ID_INTEL_IOAT_HSW4 0x2f24 40 #define PCI_DEVICE_ID_INTEL_IOAT_HSW5 0x2f25 41 #define PCI_DEVICE_ID_INTEL_IOAT_HSW6 0x2f26 42 #define PCI_DEVICE_ID_INTEL_IOAT_HSW7 0x2f27 43 #define PCI_DEVICE_ID_INTEL_IOAT_HSW8 0x2f2e 44 #define PCI_DEVICE_ID_INTEL_IOAT_HSW9 0x2f2f 45 46 #define PCI_DEVICE_ID_INTEL_IOAT_BWD0 0x0C50 47 #define PCI_DEVICE_ID_INTEL_IOAT_BWD1 0x0C51 48 #define PCI_DEVICE_ID_INTEL_IOAT_BWD2 0x0C52 49 #define PCI_DEVICE_ID_INTEL_IOAT_BWD3 0x0C53 50 51 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE0 0x6f50 52 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE1 0x6f51 53 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE2 0x6f52 54 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE3 0x6f53 55 56 #define PCI_DEVICE_ID_INTEL_IOAT_BDX0 0x6f20 57 #define PCI_DEVICE_ID_INTEL_IOAT_BDX1 0x6f21 58 #define PCI_DEVICE_ID_INTEL_IOAT_BDX2 0x6f22 59 #define PCI_DEVICE_ID_INTEL_IOAT_BDX3 0x6f23 60 #define PCI_DEVICE_ID_INTEL_IOAT_BDX4 0x6f24 61 #define PCI_DEVICE_ID_INTEL_IOAT_BDX5 0x6f25 62 #define PCI_DEVICE_ID_INTEL_IOAT_BDX6 0x6f26 63 #define PCI_DEVICE_ID_INTEL_IOAT_BDX7 0x6f27 64 #define PCI_DEVICE_ID_INTEL_IOAT_BDX8 0x6f2e 65 #define PCI_DEVICE_ID_INTEL_IOAT_BDX9 0x6f2f 66 67 #define PCI_DEVICE_ID_INTEL_IOAT_SKX 0x2021 68 69 #define IOAT_VER_1_2 0x12 /* Version 1.2 */ 70 #define IOAT_VER_2_0 0x20 /* Version 2.0 */ 71 #define IOAT_VER_3_0 0x30 /* Version 3.0 */ 72 #define IOAT_VER_3_2 0x32 /* Version 3.2 */ 73 #define IOAT_VER_3_3 0x33 /* Version 3.3 */ 74 75 76 int system_has_dca_enabled(struct pci_dev *pdev); 77 78 struct ioat_dma_descriptor { 79 uint32_t size; 80 union { 81 uint32_t ctl; 82 struct { 83 unsigned int int_en:1; 84 unsigned int src_snoop_dis:1; 85 unsigned int dest_snoop_dis:1; 86 unsigned int compl_write:1; 87 unsigned int fence:1; 88 unsigned int null:1; 89 unsigned int src_brk:1; 90 unsigned int dest_brk:1; 91 unsigned int bundle:1; 92 unsigned int dest_dca:1; 93 unsigned int hint:1; 94 unsigned int rsvd2:13; 95 #define IOAT_OP_COPY 0x00 96 unsigned int op:8; 97 } ctl_f; 98 }; 99 uint64_t src_addr; 100 uint64_t dst_addr; 101 uint64_t next; 102 uint64_t rsv1; 103 uint64_t rsv2; 104 /* store some driver data in an unused portion of the descriptor */ 105 union { 106 uint64_t user1; 107 uint64_t tx_cnt; 108 }; 109 uint64_t user2; 110 }; 111 112 struct ioat_xor_descriptor { 113 uint32_t size; 114 union { 115 uint32_t ctl; 116 struct { 117 unsigned int int_en:1; 118 unsigned int src_snoop_dis:1; 119 unsigned int dest_snoop_dis:1; 120 unsigned int compl_write:1; 121 unsigned int fence:1; 122 unsigned int src_cnt:3; 123 unsigned int bundle:1; 124 unsigned int dest_dca:1; 125 unsigned int hint:1; 126 unsigned int rsvd:13; 127 #define IOAT_OP_XOR 0x87 128 #define IOAT_OP_XOR_VAL 0x88 129 unsigned int op:8; 130 } ctl_f; 131 }; 132 uint64_t src_addr; 133 uint64_t dst_addr; 134 uint64_t next; 135 uint64_t src_addr2; 136 uint64_t src_addr3; 137 uint64_t src_addr4; 138 uint64_t src_addr5; 139 }; 140 141 struct ioat_xor_ext_descriptor { 142 uint64_t src_addr6; 143 uint64_t src_addr7; 144 uint64_t src_addr8; 145 uint64_t next; 146 uint64_t rsvd[4]; 147 }; 148 149 struct ioat_pq_descriptor { 150 union { 151 uint32_t size; 152 uint32_t dwbes; 153 struct { 154 unsigned int rsvd:25; 155 unsigned int p_val_err:1; 156 unsigned int q_val_err:1; 157 unsigned int rsvd1:4; 158 unsigned int wbes:1; 159 } dwbes_f; 160 }; 161 union { 162 uint32_t ctl; 163 struct { 164 unsigned int int_en:1; 165 unsigned int src_snoop_dis:1; 166 unsigned int dest_snoop_dis:1; 167 unsigned int compl_write:1; 168 unsigned int fence:1; 169 unsigned int src_cnt:3; 170 unsigned int bundle:1; 171 unsigned int dest_dca:1; 172 unsigned int hint:1; 173 unsigned int p_disable:1; 174 unsigned int q_disable:1; 175 unsigned int rsvd2:2; 176 unsigned int wb_en:1; 177 unsigned int prl_en:1; 178 unsigned int rsvd3:7; 179 #define IOAT_OP_PQ 0x89 180 #define IOAT_OP_PQ_VAL 0x8a 181 #define IOAT_OP_PQ_16S 0xa0 182 #define IOAT_OP_PQ_VAL_16S 0xa1 183 unsigned int op:8; 184 } ctl_f; 185 }; 186 uint64_t src_addr; 187 uint64_t p_addr; 188 uint64_t next; 189 uint64_t src_addr2; 190 union { 191 uint64_t src_addr3; 192 uint64_t sed_addr; 193 }; 194 uint8_t coef[8]; 195 uint64_t q_addr; 196 }; 197 198 struct ioat_pq_ext_descriptor { 199 uint64_t src_addr4; 200 uint64_t src_addr5; 201 uint64_t src_addr6; 202 uint64_t next; 203 uint64_t src_addr7; 204 uint64_t src_addr8; 205 uint64_t rsvd[2]; 206 }; 207 208 struct ioat_pq_update_descriptor { 209 uint32_t size; 210 union { 211 uint32_t ctl; 212 struct { 213 unsigned int int_en:1; 214 unsigned int src_snoop_dis:1; 215 unsigned int dest_snoop_dis:1; 216 unsigned int compl_write:1; 217 unsigned int fence:1; 218 unsigned int src_cnt:3; 219 unsigned int bundle:1; 220 unsigned int dest_dca:1; 221 unsigned int hint:1; 222 unsigned int p_disable:1; 223 unsigned int q_disable:1; 224 unsigned int rsvd:3; 225 unsigned int coef:8; 226 #define IOAT_OP_PQ_UP 0x8b 227 unsigned int op:8; 228 } ctl_f; 229 }; 230 uint64_t src_addr; 231 uint64_t p_addr; 232 uint64_t next; 233 uint64_t src_addr2; 234 uint64_t p_src; 235 uint64_t q_src; 236 uint64_t q_addr; 237 }; 238 239 struct ioat_raw_descriptor { 240 uint64_t field[8]; 241 }; 242 243 struct ioat_pq16a_descriptor { 244 uint8_t coef[8]; 245 uint64_t src_addr3; 246 uint64_t src_addr4; 247 uint64_t src_addr5; 248 uint64_t src_addr6; 249 uint64_t src_addr7; 250 uint64_t src_addr8; 251 uint64_t src_addr9; 252 }; 253 254 struct ioat_pq16b_descriptor { 255 uint64_t src_addr10; 256 uint64_t src_addr11; 257 uint64_t src_addr12; 258 uint64_t src_addr13; 259 uint64_t src_addr14; 260 uint64_t src_addr15; 261 uint64_t src_addr16; 262 uint64_t rsvd; 263 }; 264 265 union ioat_sed_pq_descriptor { 266 struct ioat_pq16a_descriptor a; 267 struct ioat_pq16b_descriptor b; 268 }; 269 270 #define SED_SIZE 64 271 272 struct ioat_sed_raw_descriptor { 273 uint64_t a[8]; 274 uint64_t b[8]; 275 uint64_t c[8]; 276 }; 277 278 #endif 279