Searched refs:div0 (Results 1 – 4 of 4) sorted by relevance
| /drivers/clk/samsung/ |
| D | clk-cpu.c | 135 unsigned long div0; in exynos_set_safe_div() local
137 div0 = readl(base + E4210_DIV_CPU0); in exynos_set_safe_div()
138 div0 = (div0 & ~mask) | (div & mask); in exynos_set_safe_div()
139 writel(div0, base + E4210_DIV_CPU0); in exynos_set_safe_div()
150 unsigned long div0, div1 = 0, mux_reg; in exynos_cpuclk_pre_rate_change() local
167 div0 = cfg_data->div0; in exynos_cpuclk_pre_rate_change()
198 div0 |= alt_div; in exynos_cpuclk_pre_rate_change()
207 writel(div0, base + E4210_DIV_CPU0); in exynos_cpuclk_pre_rate_change()
246 div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK); in exynos_cpuclk_post_rate_change()
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| D | clk-cpu.h | 30 unsigned long div0; member
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| /drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | gf100.c | 270 u32 src0, div0, div1D, div1P = 0; in calc_clk() local
278 clk0 = calc_src(clk, idx, freq, &src0, &div0); in calc_clk()
293 if (div0) { in calc_clk()
295 info->ddiv |= div0 << 8; in calc_clk()
296 info->ddiv |= div0; in calc_clk()
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| D | gk104.c | 292 u32 src0, div0, div1D, div1P = 0; in calc_clk() local
300 clk0 = calc_src(clk, idx, freq, &src0, &div0); in calc_clk()
315 if (div0) { in calc_clk()
317 info->ddiv |= div0; in calc_clk()
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