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Searched refs:div_mask (Results 1 – 13 of 13) sorted by relevance

/drivers/clk/imx/
Dclk-pllv3.c45 u32 div_mask; member
104 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_recalc_rate()
132 val &= ~(pll->div_mask << pll->div_shift); in clk_pllv3_set_rate()
151 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_sys_recalc_rate()
186 val &= ~pll->div_mask; in clk_pllv3_sys_set_rate()
207 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_av_recalc_rate()
256 val &= ~pll->div_mask; in clk_pllv3_av_set_rate()
287 u32 div_mask) in imx_clk_pllv3() argument
322 pll->div_mask = div_mask; in imx_clk_pllv3()
Dclk-fixup-div.c19 #define div_mask(d) ((1 << (d->width)) - 1) macro
73 if (value > div_mask(div)) in clk_fixup_div_set_rate()
74 value = div_mask(div); in clk_fixup_div_set_rate()
79 val &= ~(div_mask(div) << div->shift); in clk_fixup_div_set_rate()
Dclk.h40 const char *parent_name, void __iomem *base, u32 div_mask);
/drivers/clk/
Dclk-divider.c33 #define div_mask(width) ((1 << (width)) - 1) macro
61 return div_mask(width); in _get_maxdiv()
63 return 1 << div_mask(width); in _get_maxdiv()
66 return div_mask(width) + 1; in _get_maxdiv()
88 return val ? val : div_mask(width) + 1; in _get_div()
113 return (div == div_mask(width) + 1) ? 0 : div; in _get_val()
146 val &= div_mask(divider->width); in clk_divider_recalc_rate()
358 bestdiv &= div_mask(divider->width); in clk_divider_round_rate()
381 return min_t(unsigned int, value, div_mask(width)); in divider_get_val()
402 val = div_mask(divider->width) << (divider->shift + 16); in clk_divider_set_rate()
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Dclk-vt8500.c32 unsigned int div_mask; member
127 u32 div = readl(cdev->div_reg) & cdev->div_mask; in vt8500_dclk_recalc_rate()
130 if ((cdev->div_mask == 0x3F) && (div & BIT(5))) in vt8500_dclk_recalc_rate()
135 div = (cdev->div_mask + 1); in vt8500_dclk_recalc_rate()
159 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { in vt8500_dclk_round_rate()
178 if (divisor == cdev->div_mask + 1) in vt8500_dclk_set_rate()
182 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { in vt8500_dclk_set_rate()
190 if (divisor > cdev->div_mask) { in vt8500_dclk_set_rate()
271 dev_clk->div_mask = 0x1f; in vtwm_device_clk_init()
273 of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask); in vtwm_device_clk_init()
/drivers/i2c/busses/
Di2c-brcmstb.c91 u32 div_mask; member
123 .div_mask = 0
128 .div_mask = 0
133 .div_mask = 0
138 .div_mask = 0
143 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
148 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
153 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
158 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
528 bsc_clk[i].div_mask); in brcmstb_i2c_set_bus_speed()
/drivers/clk/ti/
Ddivider.c31 #define div_mask(d) ((1 << ((d)->width)) - 1) macro
47 return div_mask(divider); in _get_maxdiv()
49 return 1 << div_mask(divider); in _get_maxdiv()
52 return div_mask(divider) + 1; in _get_maxdiv()
106 val &= div_mask(divider); in ti_clk_divider_recalc_rate()
227 if (value > div_mask(divider)) in ti_clk_divider_set_rate()
228 value = div_mask(divider); in ti_clk_divider_set_rate()
231 val = div_mask(divider) << (divider->shift + 16); in ti_clk_divider_set_rate()
234 val &= ~(div_mask(divider) << divider->shift); in ti_clk_divider_set_rate()
/drivers/clk/hisilicon/
Dclkdivider-hi6220.c21 #define div_mask(width) ((1 << (width)) - 1) macro
54 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
84 data &= ~(div_mask(dclk->width) << dclk->shift); in hi6220_clkdiv_set_rate()
119 max_div = div_mask(width) + 1; in hi6220_register_clkdiv()
/drivers/clk/tegra/
Dclk-divider.c26 #define div_mask(d) ((1 << (d->width)) - 1) macro
28 #define get_max_div(d) div_mask(d)
75 div = reg & div_mask(divider); in clk_frac_div_recalc_rate()
122 val &= ~(div_mask(divider) << divider->shift); in clk_frac_div_set_rate()
/drivers/sh/clk/
Dcpg.c138 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; in sh_clk_div_recalc()
154 value &= ~(clk->div_mask << clk->enable_bit); in sh_clk_div_set_rate()
167 if (clk->div_mask == SH_CLK_DIV6_MSK) { in sh_clk_div_enable()
190 val |= clk->div_mask; in sh_clk_div_disable()
/drivers/clk/samsung/
Dclk-cpu.c225 unsigned long div = 0, div_mask = DIV_MASK; in exynos_cpuclk_post_rate_change() local
247 div_mask |= E4210_DIV0_ATB_MASK; in exynos_cpuclk_post_rate_change()
250 exynos_set_safe_div(base, div, div_mask); in exynos_cpuclk_post_rate_change()
/drivers/clk/mmp/
Dclk-mix.c29 unsigned int div_mask = (1 << mix->reg_info.width_div) - 1; in _get_maxdiv() local
34 return div_mask; in _get_maxdiv()
36 return 1 << div_mask; in _get_maxdiv()
43 return div_mask + 1; in _get_maxdiv()
/drivers/mfd/
Ddb8500-prcmu.c522 u32 div_mask; member
529 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
534 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
539 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
733 u32 div_mask; in prcmu_config_clkout() local
744 div_mask = PRCM_CLKOCR_CLKODIV0_MASK; in prcmu_config_clkout()
750 div_mask = PRCM_CLKOCR_CLKODIV1_MASK; in prcmu_config_clkout()
762 if (val & div_mask) { in prcmu_config_clkout()
769 if ((val & mask & ~div_mask) != bits) { in prcmu_config_clkout()
1629 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); in dsiescclk_rate()
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