Searched refs:div_reg (Results 1 – 10 of 10) sorted by relevance
| /drivers/clk/socfpga/ |
| D | clk-periph.c | 36 if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
37 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
71 u32 div_reg[3]; in __socfpga_periph_init() local
81 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_periph_init()
83 periph_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in __socfpga_periph_init()
84 periph_clk->shift = div_reg[1]; in __socfpga_periph_init()
85 periph_clk->width = div_reg[2]; in __socfpga_periph_init()
87 periph_clk->div_reg = NULL; in __socfpga_periph_init()
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| D | clk-periph-a10.c | 39 } else if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
40 div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
81 u32 div_reg[3]; in __socfpga_periph_init() local
91 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_periph_init()
93 periph_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; in __socfpga_periph_init()
94 periph_clk->shift = div_reg[1]; in __socfpga_periph_init()
95 periph_clk->width = div_reg[2]; in __socfpga_periph_init()
97 periph_clk->div_reg = NULL; in __socfpga_periph_init()
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| D | clk-gate-a10.c | 40 else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
41 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
109 u32 div_reg[3]; in __socfpga_gate_init() local
142 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_gate_init()
144 socfpga_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; in __socfpga_gate_init()
145 socfpga_clk->shift = div_reg[1]; in __socfpga_gate_init()
146 socfpga_clk->width = div_reg[2]; in __socfpga_gate_init()
148 socfpga_clk->div_reg = NULL; in __socfpga_gate_init()
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| D | clk-gate.c | 106 else if (socfpgaclk->div_reg) { in socfpga_clk_recalc_rate()
107 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_recalc_rate()
110 if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) in socfpga_clk_recalc_rate()
183 u32 div_reg[3]; in __socfpga_gate_init() local
215 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_gate_init()
217 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in __socfpga_gate_init()
218 socfpga_clk->shift = div_reg[1]; in __socfpga_gate_init()
219 socfpga_clk->width = div_reg[2]; in __socfpga_gate_init()
221 socfpga_clk->div_reg = NULL; in __socfpga_gate_init()
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| D | clk.h | 53 void __iomem *div_reg; member
64 void __iomem *div_reg; member
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| /drivers/clk/bcm/ |
| D | clk-bcm2835.c | 629 u32 div_reg; member
679 .div_reg = CM_TIMERDIV,
690 .div_reg = CM_OTPDIV,
706 .div_reg = CM_VPUDIV,
717 .div_reg = CM_V3DDIV,
727 .div_reg = CM_ISPDIV,
737 .div_reg = CM_H264DIV,
748 .div_reg = CM_VECDIV,
758 .div_reg = CM_UARTDIV,
769 .div_reg = CM_HSMDIV,
[all …]
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| /drivers/clk/ |
| D | clk-vt8500.c | 31 void __iomem *div_reg; member
127 u32 div = readl(cdev->div_reg) & cdev->div_mask; in vt8500_dclk_recalc_rate()
198 writel(divisor, cdev->div_reg); in vt8500_dclk_set_rate()
234 u32 en_reg, div_reg; in vtwm_device_clk_init() local
264 rc = of_property_read_u32(node, "divisor-reg", &div_reg); in vtwm_device_clk_init()
266 dev_clk->div_reg = pmc_base + div_reg; in vtwm_device_clk_init()
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| /drivers/clk/hisilicon/ |
| D | clk-hi3620.c | 240 u32 div_reg; member
256 void __iomem *div_reg; member
386 val = readl_relaxed(mclk->div_reg); in mmc_clk_set_timing()
388 writel_relaxed(val, mclk->div_reg); in mmc_clk_set_timing()
448 mclk->div_reg = base + mmc_clk->div_reg; in hisi_register_clk_mmc()
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| /drivers/clk/samsung/ |
| D | clk-cpu.c | 64 static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask) in wait_until_divider_stable() argument
69 if (!(readl(div_reg) & mask)) in wait_until_divider_stable()
73 if (!(readl(div_reg) & mask)) in wait_until_divider_stable()
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| /drivers/clk/ingenic/ |
| D | cgu.c | 319 u32 div_reg, div; in ingenic_clk_recalc_rate() local
324 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
325 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()
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