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Searched refs:dpll_hw_state (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_ddi.c1284 memset(&crtc_state->dpll_hw_state, 0, in hsw_ddi_pll_select()
1285 sizeof(crtc_state->dpll_hw_state)); in hsw_ddi_pll_select()
1287 crtc_state->dpll_hw_state.wrpll = val; in hsw_ddi_pll_select()
1303 WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll)) in hsw_ddi_pll_select()
1307 spll->hw_state.spll = crtc_state->dpll_hw_state.spll; in hsw_ddi_pll_select()
1611 memset(&crtc_state->dpll_hw_state, 0, in skl_ddi_pll_select()
1612 sizeof(crtc_state->dpll_hw_state)); in skl_ddi_pll_select()
1614 crtc_state->dpll_hw_state.ctrl1 = ctrl1; in skl_ddi_pll_select()
1615 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; in skl_ddi_pll_select()
1616 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; in skl_ddi_pll_select()
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Dintel_display.c1604 u32 dpll = pipe_config->dpll_hw_state.dpll; in vlv_enable_pll()
1622 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); in vlv_enable_pll()
1665 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in chv_enable_pll()
1672 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1693 u32 dpll = crtc->config->dpll_hw_state.dpll; in i9xx_enable_pll()
1732 crtc->config->dpll_hw_state.dpll_md); in i9xx_enable_pll()
4305 if (memcmp(&crtc_state->dpll_hw_state, in intel_get_shared_dpll()
4307 sizeof(crtc_state->dpll_hw_state)) == 0) { in intel_get_shared_dpll()
4331 crtc_state->dpll_hw_state; in intel_get_shared_dpll()
6205 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); in i9xx_set_pll_dividers()
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Dintel_crt.c265 pipe_config->dpll_hw_state.wrpll = 0; in intel_crt_compute_config()
266 pipe_config->dpll_hw_state.spll = in intel_crt_compute_config()
Dintel_dsi.c489 intel_crtc->config->dpll_hw_state.dpll = in intel_dsi_pre_enable()
705 pipe_config->dpll_hw_state.dpll_md = 0; in intel_dsi_get_config()
Dintel_dp.c1116 memset(&pipe_config->dpll_hw_state, 0, in skl_edp_set_pll_config()
1117 sizeof(pipe_config->dpll_hw_state)); in skl_edp_set_pll_config()
1120 pipe_config->dpll_hw_state.cfgcr1 = 0; in skl_edp_set_pll_config()
1121 pipe_config->dpll_hw_state.cfgcr2 = 0; in skl_edp_set_pll_config()
1154 pipe_config->dpll_hw_state.ctrl1 = ctrl1; in skl_edp_set_pll_config()
1160 memset(&pipe_config->dpll_hw_state, 0, in hsw_dp_set_ddi_pll_sel()
1161 sizeof(pipe_config->dpll_hw_state)); in hsw_dp_set_ddi_pll_sel()
Dintel_drv.h420 struct intel_dpll_hw_state dpll_hw_state; member