/drivers/net/ethernet/smsc/ |
D | epic100.c | 186 #define ew32(reg, val) iowrite32(val, ioaddr + (reg)) macro 407 ew32(GENCTL, 0x4200); in epic_init_one() 411 ew32(TEST1, 0x0008); in epic_init_one() 414 ew32(MIICfg, 0x12); in epic_init_one() 416 ew32(NVCTL, (er32(NVCTL) & ~0x003c) | 0x4800); in epic_init_one() 417 ew32(GENCTL, 0x0200); in epic_init_one() 471 ew32(NVCTL, er32(NVCTL) & ~0x483c); in epic_init_one() 472 ew32(GENCTL, 0x0008); in epic_init_one() 541 ew32(INTMASK, 0x00000000); in epic_disable_int() 556 ew32(INTMASK, ep->irq_mask & ~EpicNapiEvent); in epic_napi_irq_off() [all …]
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/drivers/net/ethernet/intel/e1000e/ |
D | 82571.c | 172 ew32(EECD, eecd); in e1000_init_nvm_params_82571() 301 ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK); in e1000_init_mac_params_82571() 322 ew32(SWSM, swsm & ~E1000_SWSM_SMBI); in e1000_init_mac_params_82571() 486 ew32(SWSM, swsm | E1000_SWSM_SWESMBI); in e1000_get_hw_semaphore_82571() 517 ew32(SWSM, swsm); in e1000_put_hw_semaphore_82571() 535 ew32(EXTCNF_CTRL, extcnf_ctrl); in e1000_get_hw_semaphore_82573() 568 ew32(EXTCNF_CTRL, extcnf_ctrl); in e1000_put_hw_semaphore_82573() 625 ew32(POEMB, data); in e1000_set_d0_lplu_state_82574() 652 ew32(POEMB, data); in e1000_set_d3_lplu_state_82574() 773 ew32(HICR, E1000_HICR_FW_RESET_ENABLE); in e1000_update_nvm_checksum_82571() [all …]
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D | mac.c | 248 ew32(RAL(index), rar_low); in e1000e_rar_set_generic() 250 ew32(RAH(index), rar_high); in e1000e_rar_set_generic() 511 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); in e1000e_check_for_fiber_link() 516 ew32(CTRL, ctrl); in e1000e_check_for_fiber_link() 531 ew32(TXCW, mac->txcw); in e1000e_check_for_fiber_link() 532 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); in e1000e_check_for_fiber_link() 574 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); in e1000e_check_for_serdes_link() 579 ew32(CTRL, ctrl); in e1000e_check_for_serdes_link() 594 ew32(TXCW, mac->txcw); in e1000e_check_for_serdes_link() 595 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); in e1000e_check_for_serdes_link() [all …]
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D | nvm.c | 34 ew32(EECD, *eecd); in e1000_raise_eec_clk() 49 ew32(EECD, *eecd); in e1000_lower_eec_clk() 80 ew32(EECD, eecd); in e1000_shift_out_eec_bits() 92 ew32(EECD, eecd); in e1000_shift_out_eec_bits() 173 ew32(EECD, eecd | E1000_EECD_REQ); in e1000e_acquire_nvm() 186 ew32(EECD, eecd); in e1000e_acquire_nvm() 208 ew32(EECD, eecd); in e1000_standby_nvm() 212 ew32(EECD, eecd); in e1000_standby_nvm() 250 ew32(EECD, eecd); in e1000e_release_nvm() 270 ew32(EECD, eecd); in e1000_ready_nvm_eeprom() [all …]
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D | 80003es2lan.c | 321 ew32(SW_FW_SYNC, swfw_sync); in e1000_acquire_swfw_sync_80003es2lan() 345 ew32(SW_FW_SYNC, swfw_sync); in e1000_release_swfw_sync_80003es2lan() 695 ew32(IMC, 0xffffffff); in e1000_reset_hw_80003es2lan() 697 ew32(RCTL, 0); in e1000_reset_hw_80003es2lan() 698 ew32(TCTL, E1000_TCTL_PSP); in e1000_reset_hw_80003es2lan() 710 ew32(CTRL, ctrl | E1000_CTRL_RST); in e1000_reset_hw_80003es2lan() 729 ew32(IMC, 0xffffffff); in e1000_reset_hw_80003es2lan() 785 ew32(TXDCTL(0), reg_data); in e1000_init_hw_80003es2lan() 791 ew32(TXDCTL(1), reg_data); in e1000_init_hw_80003es2lan() 796 ew32(TCTL, reg_data); in e1000_init_hw_80003es2lan() [all …]
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D | ich8lan.c | 251 ew32(CTRL_EXT, mac_reg); in e1000_phy_is_accessible_pchlan() 273 ew32(FEXTNVM3, mac_reg); in e1000_toggle_lanphypc_pch_lpt() 279 ew32(CTRL, mac_reg); in e1000_toggle_lanphypc_pch_lpt() 283 ew32(CTRL, mac_reg); in e1000_toggle_lanphypc_pch_lpt() 344 ew32(CTRL_EXT, mac_reg); in e1000_init_phy_workarounds_pchlan() 380 ew32(CTRL_EXT, mac_reg); in e1000_init_phy_workarounds_pchlan() 943 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); in e1000_k1_workaround_lpt_lp() 987 ew32(FEXTNVM6, fextnvm6); in e1000_k1_workaround_lpt_lp() 1084 ew32(LTRV, reg); in e1000_platform_pm_pch_lpt() 1118 ew32(H2ME, mac_reg); in e1000_enable_ulp_lpt_lp() [all …]
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D | netdev.c | 632 ew32(RCTL, rctl & ~E1000_RCTL_EN); in e1000e_update_rdt_wa() 649 ew32(TCTL, tctl & ~E1000_TCTL_EN); in e1000e_update_tdt_wa() 1112 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); in e1000_print_hw_hang() 1118 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); in e1000_print_hw_hang() 1789 ew32(RCTL, rctl & ~E1000_RCTL_EN); in e1000_intr_msi() 1870 ew32(RCTL, rctl & ~E1000_RCTL_EN); in e1000_intr() 1916 ew32(IMS, E1000_IMS_OTHER); in e1000_msix_other() 1921 ew32(ICS, (icr & adapter->eiac_mask)); in e1000_msix_other() 1934 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER); in e1000_msix_other() 1951 ew32(ICS, tx_ring->ims_val); in e1000_intr_msix_tx() [all …]
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D | ethtool.c | 850 ew32(STATUS, toggle); in e1000_reg_test() 859 ew32(STATUS, before); in e1000_reg_test() 1015 ew32(IMC, 0xFFFFFFFF); in e1000_intr_test() 1046 ew32(IMC, mask); in e1000_intr_test() 1047 ew32(ICS, mask); in e1000_intr_test() 1064 ew32(IMS, mask); in e1000_intr_test() 1065 ew32(ICS, mask); in e1000_intr_test() 1082 ew32(IMC, ~mask & 0x00007FFF); in e1000_intr_test() 1083 ew32(ICS, ~mask & 0x00007FFF); in e1000_intr_test() 1095 ew32(IMC, 0xFFFFFFFF); in e1000_intr_test() [all …]
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D | phy.c | 154 ew32(MDIC, mdic); in e1000e_read_phy_reg_mdic() 218 ew32(MDIC, mdic); in e1000e_write_phy_reg_mdic() 485 ew32(KMRNCTRLSTA, kmrnctrlsta); in __e1000_read_kmrn_reg() 558 ew32(KMRNCTRLSTA, kmrnctrlsta); in __e1000_write_kmrn_reg() 1480 ew32(CTRL, ctrl); in e1000e_phy_force_speed_duplex_setup() 2125 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); in e1000e_phy_hw_reset_generic() 2130 ew32(CTRL, ctrl); in e1000e_phy_hw_reset_generic()
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D | ptp.c | 74 ew32(TIMINCA, timinca); in e1000e_phc_adjfreq()
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D | manage.c | 297 ew32(HICR, hicr | E1000_HICR_C); in e1000e_mng_write_dhcp_info()
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D | e1000.h | 590 #define ew32(reg, val) __ew32(hw, E1000_##reg, (val)) macro
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/drivers/net/ethernet/intel/e1000/ |
D | e1000_hw.c | 418 ew32(IMC, 0xffffffff); in e1000_reset_hw() 424 ew32(RCTL, 0); in e1000_reset_hw() 425 ew32(TCTL, E1000_TCTL_PSP); in e1000_reset_hw() 440 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST)); in e1000_reset_hw() 467 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST)); in e1000_reset_hw() 471 ew32(CTRL, (ctrl | E1000_CTRL_RST)); in e1000_reset_hw() 488 ew32(CTRL_EXT, ctrl_ext); in e1000_reset_hw() 512 ew32(MANC, manc); in e1000_reset_hw() 522 ew32(LEDCTL, led_ctrl); in e1000_reset_hw() 527 ew32(IMC, 0xffffffff); in e1000_reset_hw() [all …]
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D | e1000_ethtool.c | 751 ew32(STATUS, toggle); in e1000_reg_test() 760 ew32(STATUS, before); in e1000_reg_test() 870 ew32(IMC, 0xFFFFFFFF); in e1000_intr_test() 887 ew32(IMC, mask); in e1000_intr_test() 888 ew32(ICS, mask); in e1000_intr_test() 905 ew32(IMS, mask); in e1000_intr_test() 906 ew32(ICS, mask); in e1000_intr_test() 923 ew32(IMC, ~mask & 0x00007FFF); in e1000_intr_test() 924 ew32(ICS, ~mask & 0x00007FFF); in e1000_intr_test() 936 ew32(IMC, 0xFFFFFFFF); in e1000_intr_test() [all …]
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D | e1000_main.c | 313 ew32(IMC, ~0); in e1000_irq_disable() 326 ew32(IMS, IMS_ENABLE_MASK); in e1000_irq_enable() 368 ew32(MANC, manc); in e1000_init_manageability() 382 ew32(MANC, manc); in e1000_release_manageability() 430 ew32(ICS, E1000_ICS_LSC); in e1000_up() 526 ew32(RCTL, rctl & ~E1000_RCTL_EN); in e1000_down() 534 ew32(TCTL, tctl); in e1000_down() 633 ew32(PBA, pba); in e1000_reset() 685 ew32(PBA, pba); in e1000_reset() 708 ew32(WUC, 0); in e1000_reset() [all …]
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D | e1000_osdep.h | 58 #define ew32(reg, value) \ macro
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/drivers/net/ethernet/intel/igbvf/ |
D | netdev.c | 884 ew32(EIMS, adapter->eims_other); in igbvf_msix_other() 910 ew32(EICS, tx_ring->eims_value); in igbvf_intr_msix_tx() 912 ew32(EIMS, tx_ring->eims_value); in igbvf_intr_msix_tx() 1015 ew32(IVAR_MISC, tmp); in igbvf_configure_msix() 1179 ew32(EIMC, ~0); in igbvf_irq_disable() 1182 ew32(EIAC, 0); in igbvf_irq_disable() 1193 ew32(EIAC, adapter->eims_enable_mask); in igbvf_irq_enable() 1194 ew32(EIAM, adapter->eims_enable_mask); in igbvf_irq_enable() 1195 ew32(EIMS, adapter->eims_enable_mask); in igbvf_irq_enable() 1220 ew32(EIMS, adapter->rx_ring->eims_value); in igbvf_poll() [all …]
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D | mbx.c | 239 ew32(V2PMAILBOX(0), E1000_V2PMAILBOX_VFU); in e1000_obtain_mbx_lock_vf() 278 ew32(V2PMAILBOX(0), E1000_V2PMAILBOX_REQ); in e1000_write_mbx_vf() 307 ew32(V2PMAILBOX(0), E1000_V2PMAILBOX_ACK); in e1000_read_mbx_vf()
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D | regs.h | 100 #define ew32(reg, val) writel((val), hw->hw_addr + E1000_##reg) macro
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D | vf.c | 133 ew32(CTRL, ctrl | E1000_CTRL_RST); in e1000_reset_hw_vf()
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