| /drivers/clk/zynq/ |
| D | pll.c | 66 u32 fbdiv; in zynq_pll_round_rate() local
68 fbdiv = DIV_ROUND_CLOSEST(rate, *prate); in zynq_pll_round_rate()
69 if (fbdiv < PLL_FBDIV_MIN) in zynq_pll_round_rate()
70 fbdiv = PLL_FBDIV_MIN; in zynq_pll_round_rate()
71 else if (fbdiv > PLL_FBDIV_MAX) in zynq_pll_round_rate()
72 fbdiv = PLL_FBDIV_MAX; in zynq_pll_round_rate()
74 return *prate * fbdiv; in zynq_pll_round_rate()
87 u32 fbdiv; in zynq_pll_recalc_rate() local
93 fbdiv = (clk_readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >> in zynq_pll_recalc_rate()
96 return parent_rate * fbdiv; in zynq_pll_recalc_rate()
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| /drivers/clk/pistachio/ |
| D | clk-pll.c | 214 vco *= (params->fbdiv << 24) + params->frac; in pll_gf40lp_frac_set_rate()
233 (params->fbdiv << PLL_CTRL1_FBDIV_SHIFT); in pll_gf40lp_frac_set_rate()
276 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; in pll_gf40lp_frac_recalc_rate() local
280 fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK; in pll_gf40lp_frac_recalc_rate()
292 rate *= (fbdiv << 24) + frac; in pll_gf40lp_frac_recalc_rate()
294 rate *= (fbdiv << 24); in pll_gf40lp_frac_recalc_rate()
369 vco = div_u64(params->fref * params->fbdiv, params->refdiv); in pll_gf40lp_laint_set_rate()
401 (params->fbdiv << PLL_CTRL1_FBDIV_SHIFT) | in pll_gf40lp_laint_set_rate()
416 u32 val, prediv, fbdiv, postdiv1, postdiv2; in pll_gf40lp_laint_recalc_rate() local
421 fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK; in pll_gf40lp_laint_recalc_rate()
[all …]
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| D | clk.h | 101 unsigned long long fbdiv; member
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| /drivers/clk/berlin/ |
| D | berlin2-pll.c | 57 u32 val, fbdiv, rfdiv, vcodivsel, vcodiv; in berlin2_pll_recalc_rate() local
61 fbdiv = (val >> map->fbdiv_shift) & FBDIV_MASK; in berlin2_pll_recalc_rate()
77 rate *= fbdiv * map->mult; in berlin2_pll_recalc_rate()
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| D | berlin2-avpll.c | 170 u32 reg, refdiv, fbdiv; in berlin2_avpll_vco_recalc_rate() local
177 fbdiv = (reg & VCO_FBDIV_MASK) >> VCO_FBDIV_SHIFT; in berlin2_avpll_vco_recalc_rate()
178 freq *= fbdiv; in berlin2_avpll_vco_recalc_rate()
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| /drivers/gpu/drm/radeon/ |
| D | rv740_dpm.c | 134 u32 fbdiv; in rv740_populate_sclk_value() local
146 fbdiv = (u32) tmp; in rv740_populate_sclk_value()
156 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); in rv740_populate_sclk_value()
166 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); in rv740_populate_sclk_value()
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| D | rv730_dpm.c | 54 u32 fbdiv; in rv730_populate_sclk_value() local
72 fbdiv = (u32) tmp; in rv730_populate_sclk_value()
88 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); in rv730_populate_sclk_value()
98 u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000); in rv730_populate_sclk_value()
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| D | rs780_dpm.c | 211 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in rs780_preset_starting_fbdiv() local
213 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv), in rs780_preset_starting_fbdiv()
216 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv), in rs780_preset_starting_fbdiv()
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| D | rv770_dpm.c | 503 u32 fbdiv; in rv770_populate_sclk_value() local
520 fbdiv = (u32) tmp; in rv770_populate_sclk_value()
535 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); in rv770_populate_sclk_value()
545 u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000); in rv770_populate_sclk_value()
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| D | ni_dpm.c | 2014 u32 fbdiv; in ni_calculate_sclk_params() local
2027 fbdiv = (u32) tmp; in ni_calculate_sclk_params()
2037 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); in ni_calculate_sclk_params()
2047 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); in ni_calculate_sclk_params()
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| D | si_dpm.c | 4848 u32 fbdiv; in si_calculate_sclk_params() local
4860 fbdiv = (u32) tmp; in si_calculate_sclk_params()
4870 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); in si_calculate_sclk_params()
4880 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); in si_calculate_sclk_params()
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| D | ci_dpm.c | 3147 u32 fbdiv; in ci_calculate_sclk_params() local
3157 fbdiv = dividers.fb_div & 0x3FFFFFF; in ci_calculate_sclk_params()
3160 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); in ci_calculate_sclk_params()
3170 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); in ci_calculate_sclk_params()
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| /drivers/clk/ |
| D | clk-axm5516.c | 55 unsigned long rate, fbdiv, refdiv, postdiv; in axxia_pllclk_recalc() local
60 fbdiv = ((control >> 4) & 0xfff) + 3; in axxia_pllclk_recalc()
62 rate = (parent_rate / (refdiv * postdiv)) * fbdiv; in axxia_pllclk_recalc()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | ci_dpm.c | 3285 u32 fbdiv; in ci_calculate_sclk_params() local
3295 fbdiv = dividers.fb_div & 0x3FFFFFF; in ci_calculate_sclk_params()
3298 spll_func_cntl_3 |= (fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT); in ci_calculate_sclk_params()
3308 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); in ci_calculate_sclk_params()
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