| /drivers/video/fbdev/matrox/ |
| D | matroxfb_g450.c | 243 u_int32_t hfp; in computeRegs() local
285 hfp = (((outd->h_f_porch + pixclock) / pixclock)) & ~1; in computeRegs()
287 hlen = hvis + hfp + hsl + hbp; in computeRegs()
290 dprintk(KERN_DEBUG "WL: vis=%u, hf=%u, hs=%u, hb=%u, total=%u\n", hvis, hfp, hsl, hbp, hlen); in computeRegs()
293 hfp -= over; in computeRegs()
297 hfp += 4; in computeRegs()
300 hfp += 16; in computeRegs()
309 r->regs[0x2C] = hfp; in computeRegs()
313 …dprintk(KERN_DEBUG "PG: vis=%04X, hf=%02X, hs=%02X, hb=%02X, total=%04X\n", hvis, hfp, hsl, hbp, h… in computeRegs()
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| /drivers/gpu/drm/tilcdc/ |
| D | tilcdc_crtc.c | 265 uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw; in tilcdc_crtc_mode_set() local
303 hfp = mode->hsync_start - mode->hdisplay; in tilcdc_crtc_mode_set()
310 mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw); in tilcdc_crtc_mode_set()
324 reg |= ((hfp-1) & 0x300) >> 8; in tilcdc_crtc_mode_set()
332 (((hfp-1) & 0xff) << 16) | in tilcdc_crtc_mode_set()
471 uint32_t hbp, hfp, hsw, vbp, vfp, vsw; in tilcdc_crtc_mode_valid() local
492 hfp = mode->hsync_start - mode->hdisplay; in tilcdc_crtc_mode_valid()
503 if ((hfp-1) & ~0x3ff) { in tilcdc_crtc_mode_valid()
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| /drivers/video/fbdev/omap2/dss/ |
| D | dsi.c | 3463 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div; in dsi_config_cmd_mode_interleaving() local
3485 hfp = FLD_GET(r, 23, 12); in dsi_config_cmd_mode_interleaving()
3509 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl); in dsi_config_cmd_mode_interleaving()
3521 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon, in dsi_config_cmd_mode_interleaving()
3524 hfp_interleave_lp = dsi_compute_interleave_lp(hfp, in dsi_config_cmd_mode_interleaving()
3712 int hfp = dsi->vm_timings.hfp; in dsi_proto_timings() local
3730 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp + in dsi_proto_timings()
3734 hfp, hsync_end ? hsa : 0, tl); in dsi_proto_timings()
3740 r = FLD_MOD(r, hfp, 23, 12); /* HFP */ in dsi_proto_timings()
4345 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp; in print_dsi_vm()
[all …]
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| D | hdmi_wp.c | 172 timing_h |= FLD_VAL(timings->hfp, 19, 8); in hdmi_wp_video_config_timing()
194 timings->hfp = param->timings.hfp; in hdmi_wp_init_vid_fmt_timings()
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| D | hdmi5_core.c | 301 video_cfg->v_fc_config.timings.hfp = cfg->timings.hfp; in hdmi_core_init()
302 video_cfg->hblank = cfg->timings.hfp + in hdmi_core_init()
359 cfg->v_fc_config.timings.hfp >> 8, 4, 0); in hdmi_core_video_config()
361 cfg->v_fc_config.timings.hfp & 0xFF, 7, 0); in hdmi_core_video_config()
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| D | display.c | 278 ovt->hfp = vm->hfront_porch; in videomode_to_omap_video_timings()
311 vm->hfront_porch = ovt->hfp; in omap_video_timings_to_videomode()
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| D | display-sysfs.c | 109 t.x_res, t.hfp, t.hbp, t.hsw, in display_timings_show()
134 &t.x_res, &t.hfp, &t.hbp, &t.hsw, in display_timings_store()
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| D | dispc.c | 2115 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width; in check_horiz_timing_omap3()
2122 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk); in check_horiz_timing_omap3()
3034 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp, in _dispc_lcd_timings_ok() argument
3038 hfp < 1 || hfp > dispc.feat->hp_max || in _dispc_lcd_timings_ok()
3070 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp, in dispc_mgr_timings_ok()
3080 int hfp, int hbp, int vsw, int vfp, int vbp, in _dispc_mgr_set_lcd_timings() argument
3092 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3204 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw, in dispc_mgr_set_timings()
3208 xtot = t.x_res + t.hfp + t.hsw + t.hbp; in dispc_mgr_set_timings()
3216 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp); in dispc_mgr_set_timings()
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| D | venc.c | 271 .hfp = 12,
292 .hfp = 16,
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| /drivers/gpu/drm/fsl-dcu/ |
| D | fsl_dcu_drm_crtc.c | 87 unsigned int hbp, hfp, hsw, vbp, vfp, vsw, div, index; in fsl_dcu_drm_crtc_mode_set_nofb() local
97 hfp = mode->hsync_start - mode->hdisplay; in fsl_dcu_drm_crtc_mode_set_nofb()
106 DCU_HSYN_PARA_FP(hfp)); in fsl_dcu_drm_crtc_mode_set_nofb()
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| /drivers/video/fbdev/omap/ |
| D | lcd_inn1510.c | 66 .hfp = 40,
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| D | lcd_htcherald.c | 72 .hfp = 10,
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| D | lcd_palmte.c | 64 .hfp = 8,
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| D | lcd_palmtt.c | 70 .hfp = 8,
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| D | lcd_palmz71.c | 65 .hfp = 8,
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| D | lcd_osk.c | 87 .hfp = 40,
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| D | lcd_h3.c | 81 .hfp = 14,
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| D | lcd_inn1610.c | 87 .hfp = 40,
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| D | lcd_ams_delta.c | 154 .hfp = 1,
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| D | omapfb.h | 81 int hfp; /* Horizontal front porch */ member
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| /drivers/gpu/drm/i915/ |
| D | intel_dsi.c | 779 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; in set_dsi_timings() local
782 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; in set_dsi_timings()
790 hfp /= 2; in set_dsi_timings()
802 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); in set_dsi_timings()
824 I915_WRITE(MIPI_HFP_COUNT(port), hfp); in set_dsi_timings()
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| D | intel_dsi_pll.c | 81 u32 hactive, vactive, hfp, hsync, hbp, vfp, vsync, vbp; in dsi_rr_formula() local
93 hfp = mode->hsync_start - mode->hdisplay; in dsi_rr_formula()
104 hfp_bytes = DIV_ROUND_UP(hfp * bpp, 8); in dsi_rr_formula()
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| /drivers/gpu/drm/omapdrm/ |
| D | omap_connector.c | 52 mode->hsync_start = mode->hdisplay + timings->hfp; in copy_timings_omap_to_drm()
83 timings->hfp = mode->hsync_start - mode->hdisplay; in copy_timings_drm_to_omap()
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| /drivers/media/platform/sti/bdisp/ |
| D | bdisp-reg.h | 48 u32 hfp; member
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| /drivers/gpu/drm/tegra/ |
| D | dsi.c | 501 unsigned int hact, hsw, hbp, hfp, i, mul, div; in tegra_dsi_configure() local
571 hfp = (mode->hsync_start - mode->hdisplay) * mul / div; in tegra_dsi_configure()
576 hfp -= 8; in tegra_dsi_configure()
580 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5); in tegra_dsi_configure()
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