Home
last modified time | relevance | path

Searched refs:hsync_start (Results 1 – 25 of 81) sorted by relevance

1234

/drivers/gpu/drm/panel/
Dpanel-simple.c377 .hsync_start = 800 + 0,
402 .hsync_start = 1024 + 156,
425 .hsync_start = 1280 + 119,
448 .hsync_start = 1366 + 20,
472 .hsync_start = 1366 + 40,
495 .hsync_start = 1366 + 48,
518 .hsync_start = 1920 + 172,
546 .hsync_start = 1024 + 160,
574 .hsync_start = 1366 + 58,
597 .hsync_start = 1366 + 48,
[all …]
/drivers/gpu/drm/
Ddrm_modes.c55 mode->hdisplay, mode->hsync_start, in drm_mode_debug_printmodeline()
284 drm_mode->hsync_start = drm_mode->hsync_end - in drm_cvt_mode()
286 drm_mode->hsync_start += CVT_H_GRANULARITY - in drm_cvt_mode()
287 drm_mode->hsync_start % CVT_H_GRANULARITY; in drm_cvt_mode()
319 drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC; in drm_cvt_mode()
509 drm_mode->hsync_start = hdisplay_rnd + hfront_porch; in drm_gtf_mode_complex()
510 drm_mode->hsync_end = drm_mode->hsync_start + hsync; in drm_gtf_mode_complex()
588 dmode->hsync_start = dmode->hdisplay + vm->hfront_porch; in drm_display_mode_from_videomode()
589 dmode->hsync_end = dmode->hsync_start + vm->hsync_len; in drm_display_mode_from_videomode()
629 vm->hfront_porch = dmode->hsync_start - dmode->hdisplay; in drm_display_mode_to_videomode()
[all …]
/drivers/gpu/drm/gma500/
Dmdfld_tpo_vid.c44 mode->hsync_start = mode->hdisplay + in tpo_vid_get_config_mode()
47 mode->hsync_end = mode->hsync_start + in tpo_vid_get_config_mode()
64 dev_dbg(dev->dev, "HSS is %d\n", mode->hsync_start); in tpo_vid_get_config_mode()
74 mode->hsync_start = 873; in tpo_vid_get_config_mode()
Dmdfld_tmd_vid.c47 mode->hsync_start = mode->hdisplay + \ in tmd_vid_get_config_mode()
50 mode->hsync_end = mode->hsync_start + \ in tmd_vid_get_config_mode()
67 dev_dbg(dev->dev, "HSS is %d\n", mode->hsync_start); in tmd_vid_get_config_mode()
77 mode->hsync_start = 487; in tmd_vid_get_config_mode()
Doaktrail_lvds.c240 mode->hsync_start = mode->hdisplay + \ in oaktrail_lvds_get_configuration_mode()
243 mode->hsync_end = mode->hsync_start + \ in oaktrail_lvds_get_configuration_mode()
260 printk(KERN_INFO "HSS is %d\n", mode->hsync_start); in oaktrail_lvds_get_configuration_mode()
Dmdfld_dsi_dpi.c436 pclk_hfp = mode->hsync_start - mode->hdisplay; in mdfld_dsi_dpi_timing_calculation()
437 pclk_hsync = mode->hsync_end - mode->hsync_start; in mdfld_dsi_dpi_timing_calculation()
697 adjusted_mode->hsync_start = fixed_mode->hsync_start; in mdfld_dsi_dpi_mode_fixup()
800 ((mode->hsync_end - 1) << 16) | (mode->hsync_start - 1)); in mdfld_set_pipe_timing()
/drivers/gpu/drm/msm/mdp/mdp5/
Dmdp5_encoder.c142 mode->hdisplay, mode->hsync_start, in mdp5_encoder_mode_set()
183 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp5_encoder_mode_set()
184 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp5_encoder_mode_set()
197 display_v_start += mode->htotal - mode->hsync_start; in mdp5_encoder_mode_set()
198 display_v_end -= mode->hsync_start - mode->hdisplay; in mdp5_encoder_mode_set()
204 MDP5_INTF_HSYNC_CTL_PULSEW(mode->hsync_end - mode->hsync_start) | in mdp5_encoder_mode_set()
/drivers/gpu/drm/omapdrm/
Domap_connector.c52 mode->hsync_start = mode->hdisplay + timings->hfp; in copy_timings_omap_to_drm()
53 mode->hsync_end = mode->hsync_start + timings->hsw; in copy_timings_omap_to_drm()
83 timings->hfp = mode->hsync_start - mode->hdisplay; in copy_timings_drm_to_omap()
84 timings->hsw = mode->hsync_end - mode->hsync_start; in copy_timings_drm_to_omap()
247 mode->hdisplay, mode->hsync_start, in omap_connector_mode_valid()
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_encoders.c154 unsigned hover = native_mode->hsync_start - native_mode->hdisplay; in amdgpu_panel_mode_fixup()
156 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start; in amdgpu_panel_mode_fixup()
166 adjusted_mode->hsync_start = native_mode->hdisplay + hover; in amdgpu_panel_mode_fixup()
167 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width; in amdgpu_panel_mode_fixup()
/drivers/gpu/drm/sti/
Dsti_vtg.c167 tmp = (mode->hsync_end - mode->hsync_start + HDMI_DELAY) << 16; in vtg_set_mode()
182 tmp = (mode->hsync_end - mode->hsync_start) << 16; in vtg_set_mode()
193 tmp = (mode->hsync_end - mode->hsync_start + AWG_DELAY_HD) << 16; in vtg_set_mode()
208 tmp = (mode->hsync_end - mode->hsync_start) << 16; in vtg_set_mode()
279 return mode.htotal - mode.hsync_start + x; in sti_vtg_get_pixel_number()
/drivers/gpu/drm/msm/mdp/mdp4/
Dmdp4_dtv_encoder.c119 mode->hdisplay, mode->hsync_start, in mdp4_dtv_encoder_mode_set()
138 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp4_dtv_encoder_mode_set()
139 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_dtv_encoder_mode_set()
147 MDP4_DTV_HSYNC_CTRL_PULSEW(mode->hsync_end - mode->hsync_start) | in mdp4_dtv_encoder_mode_set()
Dmdp4_lcdc_encoder.c285 mode->hdisplay, mode->hsync_start, in mdp4_lcdc_encoder_mode_set()
304 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp4_lcdc_encoder_mode_set()
305 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_lcdc_encoder_mode_set()
313 MDP4_LCDC_HSYNC_CTRL_PULSEW(mode->hsync_end - mode->hsync_start) | in mdp4_lcdc_encoder_mode_set()
/drivers/gpu/drm/radeon/
Dradeon_encoders.c328 unsigned hover = native_mode->hsync_start - native_mode->hdisplay; in radeon_panel_mode_fixup()
330 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start; in radeon_panel_mode_fixup()
342 adjusted_mode->hsync_start = native_mode->hdisplay + hover; in radeon_panel_mode_fixup()
343 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width; in radeon_panel_mode_fixup()
Dradeon_legacy_crtc.c56 int hsync_start; in radeon_legacy_rmx_mode_set() local
86 hsync_start = mode->crtc_hsync_start - 8; in radeon_legacy_rmx_mode_set()
88 fp_h_sync_strt_wid = ((hsync_start & 0x1fff) in radeon_legacy_rmx_mode_set()
583 int hsync_start; in radeon_set_crtc_timing() local
630 hsync_start = mode->crtc_hsync_start - 8; in radeon_set_crtc_timing()
632 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) in radeon_set_crtc_timing()
/drivers/gpu/drm/shmobile/
Dshmob_drm_crtc.c112 value = (((mode->hsync_end - mode->hsync_start) / 8) << 16) /* HSYNW */ in shmob_drm_crtc_setup_geometry()
113 | (mode->hsync_start / 8); /* HSYNP */ in shmob_drm_crtc_setup_geometry()
117 | (((mode->hsync_end - mode->hsync_start) & 7) << 8) in shmob_drm_crtc_setup_geometry()
118 | (mode->hsync_start & 7); in shmob_drm_crtc_setup_geometry()
660 mode->hsync_start = sdev->pdata->panel.mode.hsync_start; in shmob_drm_connector_get_modes()
/drivers/gpu/drm/tilcdc/
Dtilcdc_crtc.c231 adjusted_mode->hskew = mode->hsync_end - mode->hsync_start; in tilcdc_crtc_mode_fixup()
303 hfp = mode->hsync_start - mode->hdisplay; in tilcdc_crtc_mode_set()
304 hsw = mode->hsync_end - mode->hsync_start; in tilcdc_crtc_mode_set()
492 hfp = mode->hsync_start - mode->hdisplay; in tilcdc_crtc_mode_valid()
493 hsw = mode->hsync_end - mode->hsync_start; in tilcdc_crtc_mode_valid()
/drivers/gpu/drm/fsl-dcu/
Dfsl_dcu_drm_crtc.c97 hfp = mode->hsync_start - mode->hdisplay; in fsl_dcu_drm_crtc_mode_set_nofb()
98 hsw = mode->hsync_end - mode->hsync_start; in fsl_dcu_drm_crtc_mode_set_nofb()
/drivers/media/platform/xilinx/
Dxilinx-vtc.h26 unsigned int hsync_start; member
/drivers/gpu/drm/msm/hdmi/
Dhdmi_bridge.c155 hstart = mode->htotal - mode->hsync_start; in hdmi_bridge_mode_set()
156 hend = mode->htotal - mode->hsync_start + mode->hdisplay; in hdmi_bridge_mode_set()
/drivers/gpu/drm/rcar-du/
Drcar_du_crtc.c157 rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19); in rcar_du_crtc_set_display_timing()
158 rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start + in rcar_du_crtc_set_display_timing()
161 mode->hsync_start - 1); in rcar_du_crtc_set_display_timing()
174 rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start - 1); in rcar_du_crtc_set_display_timing()
/drivers/video/adf/
Dadf_fbdev.c132 vmode->right_margin = mode->hsync_start - mode->hdisplay; in adf_modeinfo_to_fb_videomode()
135 vmode->hsync_len = mode->hsync_end - mode->hsync_start; in adf_modeinfo_to_fb_videomode()
162 mode->hsync_start = mode->hdisplay + vmode->right_margin; in adf_modeinfo_from_fb_videomode()
163 mode->hsync_end = mode->hsync_start + vmode->hsync_len; in adf_modeinfo_from_fb_videomode()
/drivers/video/fbdev/
Dgbefb.c528 timing->hsync_start = var->xres + var->right_margin + 1; in compute_gbe_timing()
529 timing->hsync_end = timing->hsync_start + var->hsync_len; in compute_gbe_timing()
564 SET_GBE_FIELD(VT_HSYNC, HSYNC_ON, val, timing->hsync_start); in gbe_set_timing_info()
993 var->right_margin = timing.hsync_start - timing.width; in gbefb_check_var()
996 var->hsync_len = timing.hsync_end - timing.hsync_start; in gbefb_check_var()
/drivers/gpu/drm/msm/edp/
Dedp_bridge.c66 mode->hdisplay, mode->hsync_start, in edp_bridge_mode_set()
/drivers/gpu/drm/exynos/
Dexynos_hdmi.c1311 val = (m->hsync_start - m->hdisplay - 2); in hdmi_v13_mode_apply()
1342 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay)); in hdmi_v13_mode_apply()
1344 (m->hsync_start - m->hdisplay)) << 12; in hdmi_v13_mode_apply()
1425 (m->htotal / 2) + (m->hsync_start - m->hdisplay)); in hdmi_v14_mode_apply()
1427 (m->htotal / 2) + (m->hsync_start - m->hdisplay)); in hdmi_v14_mode_apply()
1469 m->hsync_start - m->hdisplay - 2); in hdmi_v14_mode_apply()
/drivers/video/fbdev/vermilion/
Dvermilion.c781 u32 htotal, hactive, hblank_start, hblank_end, hsync_start, hsync_end; in vmlfb_set_par_locked() local
798 hsync_start = hactive + var->right_margin; in vmlfb_set_par_locked()
799 hsync_end = hsync_start + var->hsync_len; in vmlfb_set_par_locked()
847 ((hsync_end - 1) << 16) | (hsync_start - 1)); in vmlfb_set_par_locked()

1234