| /drivers/gpu/drm/amd/amdgpu/ |
| D | cz_ih.c | 60 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_enable_interrupts() local
63 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); in cz_ih_enable_interrupts()
65 WREG32(mmIH_CNTL, ih_cntl); in cz_ih_enable_interrupts()
80 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_disable_interrupts() local
83 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); in cz_ih_disable_interrupts()
85 WREG32(mmIH_CNTL, ih_cntl); in cz_ih_disable_interrupts()
108 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in cz_ih_irq_init() local
148 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_irq_init()
149 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0); in cz_ih_irq_init()
152 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1); in cz_ih_irq_init()
[all …]
|
| D | iceland_ih.c | 60 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_enable_interrupts() local
63 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); in iceland_ih_enable_interrupts()
65 WREG32(mmIH_CNTL, ih_cntl); in iceland_ih_enable_interrupts()
80 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_disable_interrupts() local
83 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); in iceland_ih_disable_interrupts()
85 WREG32(mmIH_CNTL, ih_cntl); in iceland_ih_disable_interrupts()
108 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in iceland_ih_irq_init() local
148 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_irq_init()
149 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0); in iceland_ih_irq_init()
152 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1); in iceland_ih_irq_init()
[all …]
|
| D | cik_ih.c | 60 u32 ih_cntl = RREG32(mmIH_CNTL); in cik_ih_enable_interrupts() local
63 ih_cntl |= IH_CNTL__ENABLE_INTR_MASK; in cik_ih_enable_interrupts()
65 WREG32(mmIH_CNTL, ih_cntl); in cik_ih_enable_interrupts()
80 u32 ih_cntl = RREG32(mmIH_CNTL); in cik_ih_disable_interrupts() local
83 ih_cntl &= ~IH_CNTL__ENABLE_INTR_MASK; in cik_ih_disable_interrupts()
85 WREG32(mmIH_CNTL, ih_cntl); in cik_ih_disable_interrupts()
108 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in cik_ih_irq_init() local
146 ih_cntl = (0x10 << IH_CNTL__MC_WRREQ_CREDIT__SHIFT) | in cik_ih_irq_init()
151 ih_cntl |= IH_CNTL__RPTR_REARM_MASK; in cik_ih_irq_init()
152 WREG32(mmIH_CNTL, ih_cntl); in cik_ih_irq_init()
|
| /drivers/gpu/drm/radeon/ |
| D | r600.c | 3546 u32 ih_cntl = RREG32(IH_CNTL); in r600_enable_interrupts() local
3549 ih_cntl |= ENABLE_INTR; in r600_enable_interrupts()
3551 WREG32(IH_CNTL, ih_cntl); in r600_enable_interrupts()
3559 u32 ih_cntl = RREG32(IH_CNTL); in r600_disable_interrupts() local
3562 ih_cntl &= ~ENABLE_INTR; in r600_disable_interrupts()
3564 WREG32(IH_CNTL, ih_cntl); in r600_disable_interrupts()
3629 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in r600_irq_init() local
3682 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); in r600_irq_init()
3685 ih_cntl |= RPTR_REARM; in r600_irq_init()
3686 WREG32(IH_CNTL, ih_cntl); in r600_irq_init()
|
| D | si.c | 5909 u32 ih_cntl = RREG32(IH_CNTL); in si_enable_interrupts() local
5912 ih_cntl |= ENABLE_INTR; in si_enable_interrupts()
5914 WREG32(IH_CNTL, ih_cntl); in si_enable_interrupts()
5922 u32 ih_cntl = RREG32(IH_CNTL); in si_disable_interrupts() local
5925 ih_cntl &= ~ENABLE_INTR; in si_disable_interrupts()
5927 WREG32(IH_CNTL, ih_cntl); in si_disable_interrupts()
5998 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in si_irq_init() local
6048 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); in si_irq_init()
6051 ih_cntl |= RPTR_REARM; in si_irq_init()
6052 WREG32(IH_CNTL, ih_cntl); in si_irq_init()
|
| D | cik.c | 7232 u32 ih_cntl = RREG32(IH_CNTL); in cik_enable_interrupts() local
7235 ih_cntl |= ENABLE_INTR; in cik_enable_interrupts()
7237 WREG32(IH_CNTL, ih_cntl); in cik_enable_interrupts()
7252 u32 ih_cntl = RREG32(IH_CNTL); in cik_disable_interrupts() local
7255 ih_cntl &= ~ENABLE_INTR; in cik_disable_interrupts()
7257 WREG32(IH_CNTL, ih_cntl); in cik_disable_interrupts()
7357 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in cik_irq_init() local
7407 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); in cik_irq_init()
7410 ih_cntl |= RPTR_REARM; in cik_irq_init()
7411 WREG32(IH_CNTL, ih_cntl); in cik_irq_init()
|