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Searched refs:layers (Results 1 – 25 of 52) sorted by relevance

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/drivers/edac/
Dtile_edac.c128 struct edac_mc_layer layers[2]; in tile_edac_mc_probe() local
138 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in tile_edac_mc_probe()
139 layers[0].size = TILE_EDAC_NR_CSROWS; in tile_edac_mc_probe()
140 layers[0].is_virt_csrow = true; in tile_edac_mc_probe()
141 layers[1].type = EDAC_MC_LAYER_CHANNEL; in tile_edac_mc_probe()
142 layers[1].size = TILE_EDAC_NR_CHANS; in tile_edac_mc_probe()
143 layers[1].is_virt_csrow = false; in tile_edac_mc_probe()
144 mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers, in tile_edac_mc_probe()
Dpasemi_edac.c195 struct edac_mc_layer layers[2]; in pasemi_edac_probe() local
212 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in pasemi_edac_probe()
213 layers[0].size = PASEMI_EDAC_NR_CSROWS; in pasemi_edac_probe()
214 layers[0].is_virt_csrow = true; in pasemi_edac_probe()
215 layers[1].type = EDAC_MC_LAYER_CHANNEL; in pasemi_edac_probe()
216 layers[1].size = PASEMI_EDAC_NR_CHANS; in pasemi_edac_probe()
217 layers[1].is_virt_csrow = false; in pasemi_edac_probe()
218 mci = edac_mc_alloc(system_mmc_id++, ARRAY_SIZE(layers), layers, in pasemi_edac_probe()
Damd76x_edac.c239 struct edac_mc_layer layers[2]; in amd76x_probe1() local
248 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in amd76x_probe1()
249 layers[0].size = AMD76X_NR_CSROWS; in amd76x_probe1()
250 layers[0].is_virt_csrow = true; in amd76x_probe1()
251 layers[1].type = EDAC_MC_LAYER_CHANNEL; in amd76x_probe1()
252 layers[1].size = 1; in amd76x_probe1()
253 layers[1].is_virt_csrow = false; in amd76x_probe1()
254 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in amd76x_probe1()
Dhighbank_mc_edac.c160 struct edac_mc_layer layers[2]; in highbank_mc_probe() local
174 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in highbank_mc_probe()
175 layers[0].size = 1; in highbank_mc_probe()
176 layers[0].is_virt_csrow = true; in highbank_mc_probe()
177 layers[1].type = EDAC_MC_LAYER_CHANNEL; in highbank_mc_probe()
178 layers[1].size = 1; in highbank_mc_probe()
179 layers[1].is_virt_csrow = false; in highbank_mc_probe()
180 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in highbank_mc_probe()
Dr82600_edac.c273 struct edac_mc_layer layers[2]; in r82600_probe1() local
287 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in r82600_probe1()
288 layers[0].size = R82600_NR_CSROWS; in r82600_probe1()
289 layers[0].is_virt_csrow = true; in r82600_probe1()
290 layers[1].type = EDAC_MC_LAYER_CHANNEL; in r82600_probe1()
291 layers[1].size = R82600_NR_CHANS; in r82600_probe1()
292 layers[1].is_virt_csrow = false; in r82600_probe1()
293 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in r82600_probe1()
Di82860_edac.c189 struct edac_mc_layer layers[2]; in i82860_probe1() local
202 layers[0].type = EDAC_MC_LAYER_CHANNEL; in i82860_probe1()
203 layers[0].size = 2; in i82860_probe1()
204 layers[0].is_virt_csrow = true; in i82860_probe1()
205 layers[1].type = EDAC_MC_LAYER_SLOT; in i82860_probe1()
206 layers[1].size = 8; in i82860_probe1()
207 layers[1].is_virt_csrow = true; in i82860_probe1()
208 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in i82860_probe1()
Dcell_edac.c172 struct edac_mc_layer layers[2]; in cell_edac_probe() local
202 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in cell_edac_probe()
203 layers[0].size = 1; in cell_edac_probe()
204 layers[0].is_virt_csrow = true; in cell_edac_probe()
205 layers[1].type = EDAC_MC_LAYER_CHANNEL; in cell_edac_probe()
206 layers[1].size = num_chans; in cell_edac_probe()
207 layers[1].is_virt_csrow = false; in cell_edac_probe()
208 mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers, in cell_edac_probe()
Di3200_edac.c343 struct edac_mc_layer layers[2]; in i3200_probe1() local
358 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i3200_probe1()
359 layers[0].size = I3200_DIMMS; in i3200_probe1()
360 layers[0].is_virt_csrow = true; in i3200_probe1()
361 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i3200_probe1()
362 layers[1].size = nr_channels; in i3200_probe1()
363 layers[1].is_virt_csrow = false; in i3200_probe1()
364 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in i3200_probe1()
398 struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, in i3200_probe1()
Di82443bxgx_edac.c237 struct edac_mc_layer layers[2]; in i82443bxgx_edacmc_probe1() local
251 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i82443bxgx_edacmc_probe1()
252 layers[0].size = I82443BXGX_NR_CSROWS; in i82443bxgx_edacmc_probe1()
253 layers[0].is_virt_csrow = true; in i82443bxgx_edacmc_probe1()
254 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i82443bxgx_edacmc_probe1()
255 layers[1].size = I82443BXGX_NR_CHANS; in i82443bxgx_edacmc_probe1()
256 layers[1].is_virt_csrow = false; in i82443bxgx_edacmc_probe1()
257 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in i82443bxgx_edacmc_probe1()
Dsynopsys_edac.c439 struct edac_mc_layer layers[2]; in synps_edac_mc_probe() local
455 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in synps_edac_mc_probe()
456 layers[0].size = SYNPS_EDAC_NR_CSROWS; in synps_edac_mc_probe()
457 layers[0].is_virt_csrow = true; in synps_edac_mc_probe()
458 layers[1].type = EDAC_MC_LAYER_CHANNEL; in synps_edac_mc_probe()
459 layers[1].size = SYNPS_EDAC_NR_CHANS; in synps_edac_mc_probe()
460 layers[1].is_virt_csrow = false; in synps_edac_mc_probe()
462 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in synps_edac_mc_probe()
Die31200_edac.c335 struct edac_mc_layer layers[2]; in ie31200_probe1() local
349 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in ie31200_probe1()
350 layers[0].size = IE31200_DIMMS; in ie31200_probe1()
351 layers[0].is_virt_csrow = true; in ie31200_probe1()
352 layers[1].type = EDAC_MC_LAYER_CHANNEL; in ie31200_probe1()
353 layers[1].size = nr_channels; in ie31200_probe1()
354 layers[1].is_virt_csrow = false; in ie31200_probe1()
355 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in ie31200_probe1()
416 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, in ie31200_probe1()
426 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, in ie31200_probe1()
Dedac_mc.c64 edac_layer_name[mci->layers[i].type], in edac_dimm_info_location()
268 struct edac_mc_layer *layers, in edac_mc_alloc() argument
290 tot_dimms *= layers[i].size; in edac_mc_alloc()
291 if (layers[i].is_virt_csrow) in edac_mc_alloc()
292 tot_csrows *= layers[i].size; in edac_mc_alloc()
294 tot_channels *= layers[i].size; in edac_mc_alloc()
296 if (layers[i].type == EDAC_MC_LAYER_CHIP_SELECT) in edac_mc_alloc()
308 count *= layers[i].size; in edac_mc_alloc()
344 mci->layers = layer; in edac_mc_alloc()
345 memcpy(mci->layers, layers, sizeof(*layer) * n_layers); in edac_mc_alloc()
[all …]
Di82875p_edac.c393 struct edac_mc_layer layers[2]; in i82875p_probe1() local
408 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i82875p_probe1()
409 layers[0].size = I82875P_NR_CSROWS(nr_chans); in i82875p_probe1()
410 layers[0].is_virt_csrow = true; in i82875p_probe1()
411 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i82875p_probe1()
412 layers[1].size = nr_chans; in i82875p_probe1()
413 layers[1].is_virt_csrow = false; in i82875p_probe1()
414 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); in i82875p_probe1()
Di3000_edac.c316 struct edac_mc_layer layers[2]; in i3000_probe1() local
359 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i3000_probe1()
360 layers[0].size = I3000_RANKS / nr_channels; in i3000_probe1()
361 layers[0].is_virt_csrow = true; in i3000_probe1()
362 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i3000_probe1()
363 layers[1].size = nr_channels; in i3000_probe1()
364 layers[1].is_virt_csrow = false; in i3000_probe1()
365 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in i3000_probe1()
Dx38_edac.c325 struct edac_mc_layer layers[2]; in x38_probe1() local
341 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in x38_probe1()
342 layers[0].size = X38_RANKS; in x38_probe1()
343 layers[0].is_virt_csrow = true; in x38_probe1()
344 layers[1].type = EDAC_MC_LAYER_CHANNEL; in x38_probe1()
345 layers[1].size = x38_channel_num; in x38_probe1()
346 layers[1].is_virt_csrow = false; in x38_probe1()
347 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in x38_probe1()
Docteon_edac-lmc.c229 struct edac_mc_layer layers[1]; in octeon_lmc_edac_probe() local
234 layers[0].type = EDAC_MC_LAYER_CHANNEL; in octeon_lmc_edac_probe()
235 layers[0].size = 1; in octeon_lmc_edac_probe()
236 layers[0].is_virt_csrow = false; in octeon_lmc_edac_probe()
247 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt)); in octeon_lmc_edac_probe()
279 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt)); in octeon_lmc_edac_probe()
De7xxx_edac.c426 struct edac_mc_layer layers[2]; in e7xxx_probe1() local
445 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in e7xxx_probe1()
446 layers[0].size = E7XXX_NR_CSROWS; in e7xxx_probe1()
447 layers[0].is_virt_csrow = true; in e7xxx_probe1()
448 layers[1].type = EDAC_MC_LAYER_CHANNEL; in e7xxx_probe1()
449 layers[1].size = drc_chan + 1; in e7xxx_probe1()
450 layers[1].is_virt_csrow = false; in e7xxx_probe1()
451 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); in e7xxx_probe1()
Daltera_edac.c285 struct edac_mc_layer layers[2]; in altr_sdram_probe() local
361 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in altr_sdram_probe()
362 layers[0].size = 1; in altr_sdram_probe()
363 layers[0].is_virt_csrow = true; in altr_sdram_probe()
364 layers[1].type = EDAC_MC_LAYER_CHANNEL; in altr_sdram_probe()
365 layers[1].size = 1; in altr_sdram_probe()
366 layers[1].is_virt_csrow = false; in altr_sdram_probe()
367 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in altr_sdram_probe()
Di82975x_edac.c476 struct edac_mc_layer layers[2]; in i82975x_probe1() local
545 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i82975x_probe1()
546 layers[0].size = I82975X_NR_DIMMS; in i82975x_probe1()
547 layers[0].is_virt_csrow = true; in i82975x_probe1()
548 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i82975x_probe1()
549 layers[1].size = I82975X_NR_CSROWS(chans); in i82975x_probe1()
550 layers[1].is_virt_csrow = false; in i82975x_probe1()
551 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); in i82975x_probe1()
Di7300_edac.c799 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, in i7300_init_csrows()
1027 struct edac_mc_layer layers[3]; in i7300_init_one() local
1045 layers[0].type = EDAC_MC_LAYER_BRANCH; in i7300_init_one()
1046 layers[0].size = MAX_BRANCHES; in i7300_init_one()
1047 layers[0].is_virt_csrow = false; in i7300_init_one()
1048 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i7300_init_one()
1049 layers[1].size = MAX_CH_PER_BRANCH; in i7300_init_one()
1050 layers[1].is_virt_csrow = true; in i7300_init_one()
1051 layers[2].type = EDAC_MC_LAYER_SLOT; in i7300_init_one()
1052 layers[2].size = MAX_SLOTS; in i7300_init_one()
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Di5400_edac.c1190 for (channel = 0; channel < mci->layers[0].size * mci->layers[1].size; in i5400_init_dimms()
1192 for (slot = 0; slot < mci->layers[2].size; slot++) { in i5400_init_dimms()
1199 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, in i5400_init_dimms()
1266 struct edac_mc_layer layers[3]; in i5400_probe1() local
1284 layers[0].type = EDAC_MC_LAYER_BRANCH; in i5400_probe1()
1285 layers[0].size = MAX_BRANCHES; in i5400_probe1()
1286 layers[0].is_virt_csrow = false; in i5400_probe1()
1287 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i5400_probe1()
1288 layers[1].size = CHANNELS_PER_BRANCH; in i5400_probe1()
1289 layers[1].is_virt_csrow = false; in i5400_probe1()
[all …]
Dghes_edac.c84 struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, in ghes_edac_dmidecode()
419 struct edac_mc_layer layers[1]; in ghes_edac_register() local
432 layers[0].type = EDAC_MC_LAYER_ALL_MEM; in ghes_edac_register()
433 layers[0].size = num_dimm; in ghes_edac_register()
434 layers[0].is_virt_csrow = true; in ghes_edac_register()
441 mci = edac_mc_alloc(ghes_edac_mc_num, ARRAY_SIZE(layers), layers, in ghes_edac_register()
495 struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, in ghes_edac_register()
/drivers/media/dvb-frontends/
Dtc90522.c210 int layers; in tc90522s_get_frontend() local
219 layers = 0; in tc90522s_get_frontend()
246 layers = (v > 0) ? 2 : 1; in tc90522s_get_frontend()
294 stats->len = layers; in tc90522s_get_frontend()
297 for (i = 0; i < layers; i++) in tc90522s_get_frontend()
300 for (i = 0; i < layers; i++) { in tc90522s_get_frontend()
308 stats->len = layers; in tc90522s_get_frontend()
310 for (i = 0; i < layers; i++) in tc90522s_get_frontend()
313 for (i = 0; i < layers; i++) { in tc90522s_get_frontend()
346 int layers; in tc90522t_get_frontend() local
[all …]
/drivers/parisc/
Dpdc_stable.c372 for (i = 0; i < 6 && devpath->layers[i]; i++) in pdcspath_layer_read()
373 out += sprintf(out, "%u ", devpath->layers[i]); in pdcspath_layer_read()
395 unsigned int layers[6]; /* device-specific info (ctlr#, unit#, ...) */ in pdcspath_layer_write() local
408 memset(&layers, 0, sizeof(layers)); in pdcspath_layer_write()
413 layers[0] = simple_strtoul(in, NULL, 10); in pdcspath_layer_write()
414 DPRINTK("%s: layer[0]: %d\n", __func__, layers[0]); in pdcspath_layer_write()
420 layers[i] = simple_strtoul(temp, NULL, 10); in pdcspath_layer_write()
421 DPRINTK("%s: layer[%d]: %d\n", __func__, i, layers[i]); in pdcspath_layer_write()
429 memcpy(&entry->devpath.layers, &layers, sizeof(layers)); in pdcspath_layer_write()
/drivers/gpu/drm/atmel-hlcdc/
Datmel_hlcdc_dc.c54 .layers = atmel_hlcdc_at91sam9n12_layers,
138 .layers = atmel_hlcdc_at91sam9x5_layers,
241 .layers = atmel_hlcdc_sama5d3_layers,
324 .layers = atmel_hlcdc_sama5d4_layers,
393 struct atmel_hlcdc_layer *layer = dc->layers[i]; in atmel_hlcdc_dc_irq_handler()
455 dc->layers[planes->primary->layer.desc->id] = in atmel_hlcdc_dc_modeset_init()
459 dc->layers[planes->cursor->layer.desc->id] = in atmel_hlcdc_dc_modeset_init()
463 dc->layers[planes->overlays[i]->layer.desc->id] = in atmel_hlcdc_dc_modeset_init()
641 if (dc->layers[i]) in atmel_hlcdc_dc_irq_postinstall()

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